dev-arm, configs: Remove RealViewPBX platform
This is an old unused platform. We should support VExpress_GEM5 based platforms only. Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
@@ -162,7 +162,6 @@ mem_list = ObjectList(getattr(m5.objects, 'AbstractMemory', None))
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# Platform aliases. The platforms listed here might not be compiled,
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# we make sure they exist before we add them to the platform list.
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_platform_aliases_all = [
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("RealView_PBX", "RealViewPBX"),
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("VExpress_GEM5", "VExpress_GEM5_V1"),
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]
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platform_list = ObjectList(getattr(m5.objects, 'Platform', None), \
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@@ -46,7 +46,6 @@ from m5.objects.ArmSemihosting import ArmSemihosting
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class ArmMachineType(Enum):
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map = {
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'RealViewPBX' : 1901,
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'VExpress_EMM' : 2272,
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'VExpress_EMM64' : 2272,
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'DTOnly' : -1,
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@@ -613,142 +613,6 @@ class RealView(Platform):
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cpu.append(FdtPropertyWords("cpu-release-addr", \
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state.addrCells(0x8000fff8)))
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# Reference for memory map and interrupt number
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# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
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# Chapter 4: Programmer's Reference
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class RealViewPBX(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000)
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mcc = VExpressMCC()
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dcc = CoreTile2A15DCC()
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gic = Gic400(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100)
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pci_host = GenericPciHost(
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conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
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pci_pio_base=0)
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
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local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29),
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int_watchdog=ArmPPI(num=30),
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pio_addr=0x1f000600)
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clcd = Pl111(pio_addr=0x10020000, int_num=55)
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kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
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kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
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a9scu = A9SCU(pio_addr=0x1f000000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
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io_shift = 1, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0x18000000, BAR0Size = '16B',
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BAR1 = 0x18000100, BAR1Size = '1B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
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flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
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fake_mem=True)
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dmac_fake = AmbaFake(pio_addr=0x10030000)
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uart1_fake = AmbaFake(pio_addr=0x1000a000)
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uart2_fake = AmbaFake(pio_addr=0x1000b000)
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uart3_fake = AmbaFake(pio_addr=0x1000c000)
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smc_fake = AmbaFake(pio_addr=0x100e1000)
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sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0x10010000)
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gpio0_fake = AmbaFake(pio_addr=0x10013000)
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gpio1_fake = AmbaFake(pio_addr=0x10014000)
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gpio2_fake = AmbaFake(pio_addr=0x10015000)
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ssp_fake = AmbaFake(pio_addr=0x1000d000)
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sci_fake = AmbaFake(pio_addr=0x1000e000)
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aaci_fake = AmbaFake(pio_addr=0x10004000)
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mmc_fake = AmbaFake(pio_addr=0x10005000)
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rtc = PL031(pio_addr=0x10017000, int_num=42)
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energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.l2x0_fake.pio = bus.master
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self.a9scu.pio = bus.master
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self.global_timer.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, l2x0, a9scu, local_cpu_timer)
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bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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self.a9scu.pio_addr - 1),
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AddrRange(self.flash_fake.pio_addr,
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self.flash_fake.pio_addr + \
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self.flash_fake.pio_size - 1)]
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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self.a9scu.clkdomain = clkdomain
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self.local_cpu_timer.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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self.pci_host.pio = bus.master
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self.timer0.pio = bus.master
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self.timer1.pio = bus.master
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self.clcd.pio = bus.master
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self.clcd.dma = bus.slave
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self.kmi0.pio = bus.master
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self.kmi1.pio = bus.master
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self.cf_ctrl.pio = bus.master
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self.cf_ctrl.dma = bus.slave
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self.dmac_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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self.uart2_fake.pio = bus.master
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self.uart3_fake.pio = bus.master
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self.smc_fake.pio = bus.master
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self.sp810_fake.pio = bus.master
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self.watchdog_fake.pio = bus.master
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self.gpio0_fake.pio = bus.master
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self.gpio1_fake.pio = bus.master
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self.gpio2_fake.pio = bus.master
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self.ssp_fake.pio = bus.master
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self.sci_fake.pio = bus.master
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self.aaci_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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self.rtc.pio = bus.master
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self.flash_fake.pio = bus.master
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self.energy_ctrl.pio = bus.master
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.cf_ctrl.clk_domain = clkdomain
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self.dmac_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.smc_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.gpio0_fake.clk_domain = clkdomain
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self.gpio1_fake.clk_domain = clkdomain
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self.gpio2_fake.clk_domain = clkdomain
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self.ssp_fake.clk_domain = clkdomain
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self.sci_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.flash_fake.clk_domain = clkdomain
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self.energy_ctrl.clk_domain = clkdomain
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class VExpress_EMM(RealView):
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_mem_regions = [ AddrRange('2GB', size='2GB') ]
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@@ -98,13 +98,11 @@ class LinuxArmSystemBuilder(object):
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system.panic_on_oops = True
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default_kernels = {
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"RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
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"VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
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"VExpress_EMM64": "vmlinux.aarch64.20140821",
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}
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system.kernel = SysPaths.binary(default_kernels[self.machine_type])
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default_dtbs = {
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"RealViewPBX": None,
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"VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \
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.format(self.num_cpus),
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"VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
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