dev-arm: Add GICD_SGIR register

The Distributor Software Generated Interrupt Register is implemented
only if affinity routing is disabled. Since this configuration is
currently not supported in gem5, it has to be treated as RES0.

Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/gic_v3_distributor.cc

@@ -936,6 +936,10 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size,
 
         break;
 
+      case GICD_SGIR: // Error Reporting Status Register
+        // Only if affinity routing is disabled, RES0
+        break;
+
       default:
         panic("Gicv3Distributor::write(): invalid offset %#x\n", addr);
         break;

src/dev/arm/gic_v3_distributor.hh

@@ -69,6 +69,8 @@ class Gicv3Distributor : public Serializable
         GICD_IIDR = 0x0008,
         // Error Reporting Status Register
         GICD_STATUSR = 0x0010,
+        // Software Generated Interrupt Register
+        GICD_SGIR = 0x0f00,
         // Peripheral ID0 Register
         GICD_PIDR0 = 0xffe0,
         // Peripheral ID1 Register