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dev-arm: Cpu interface groupEnabled check for global enable

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Gicv3CPUInterface::groupEnabled should check for global enable flags at
distributor level:
- Gicv3Distributor.EnableGrp0
- Gicv3Distributor.EnableGrp1S
- Gicv3Distributor.EnableGrp1NS

Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-08-23 12:20:29 +01:00
parent 983f667dc3
commit 7f89594029
1 changed files with 3 additions and 3 deletions
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6
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -2276,19 +2276,19 @@ Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
case Gicv3::G0S: {
ICC_IGRPEN0_EL1 icc_igrpen0_el1 =
isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1);
return icc_igrpen0_el1.Enable;
return icc_igrpen0_el1.Enable && distributor->EnableGrp0;
}
case Gicv3::G1S: {
ICC_IGRPEN1_EL1 icc_igrpen1_el1_s =
isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S);
return icc_igrpen1_el1_s.Enable;
return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S;
}
case Gicv3::G1NS: {
ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns =
isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS);
return icc_igrpen1_el1_ns.Enable;
return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS;
}
default: