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arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking

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Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-08-20 20:48:29 +01:00
parent 34f1b771ed
commit 2a818db77a
2 changed files with 4 additions and 2 deletions
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2
src/arch/arm/miscregs.cc
View File

@@ -4646,7 +4646,7 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ICC_IGRPEN0);
InitReg(MISCREG_ICC_IGRPEN1_EL1)
.banked()
.banked64()
.mapsTo(MISCREG_ICC_IGRPEN1);
InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
.bankedChild()

4
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -191,6 +191,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
}
value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
break;
}
@@ -1358,7 +1359,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
icc_igrpen1_el3);
}
break;
setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
return;
}
// Virtual Interrupt Group 1 Enable register