dev-arm: Writes to IGRPEN1_EL3 triggering update

Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/gic_v3_cpu_interface.cc

@@ -1378,6 +1378,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
               MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
           isa->setMiscRegNoEffect(
               MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
+          updateDistributor();
           return;
       }