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dev-arm: Add read/writeBanked helpers to GICv3

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These will be used by AA64 security banked registers in GICv3.

Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-09-02 10:28:12 +01:00
parent 982a7d4f13
commit 96fdb20871
2 changed files with 16 additions and 0 deletions
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14
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -1623,6 +1623,20 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
}
}
RegVal
Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
{
return isa->readMiscRegNoEffect(
isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
}
void
Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
{
isa->setMiscRegNoEffect(
isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
}
int
Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
{

2
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -338,6 +338,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
void virtualUpdate();
RegVal bpr1(Gicv3::GroupId group);
RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
public:
Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);