dev-arm: Add resetHppi method in the GICv3 cpu interface

The method is used for resetting the highest priority pending interrupt
interrupt from the cpu interface if it matches the intid passed as an
argument.

Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/gic_v3_cpu_interface.cc

@@ -69,6 +69,13 @@ Gicv3CPUInterface::init()
     distributor = gic->getDistributor();
 }
 
+void
+Gicv3CPUInterface::resetHppi(uint32_t intid)
+{
+    if (intid == hppi.intid)
+        hppi.prio = 0xff;
+}
+
 void
 Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
 {
@@ -1843,7 +1850,7 @@ Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
     // By setting the priority to 0xff we are effectively
     // making the int_id not pending anymore at the cpu
     // interface.
-    hppi.prio = 0xff;
+    resetHppi(int_id);
     updateDistributor();
 }
 

src/dev/arm/gic_v3_cpu_interface.hh

@@ -322,6 +322,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     bool isEOISplitMode() const;
     bool isSecureBelowEL3() const;
     ICH_MISR_EL2 maintenanceInterruptStatus() const;
+    void resetHppi(uint32_t intid);
     void serialize(CheckpointOut & cp) const override;
     void unserialize(CheckpointIn & cp) override;
     void update();

src/dev/arm/gic_v3_distributor.cc

@@ -1055,7 +1055,7 @@ Gicv3Distributor::clearIrqCpuInterface(uint32_t int_id)
 {
     auto cpu_interface = route(int_id);
     if (cpu_interface)
-        cpu_interface->hppi.prio = 0xff;
+        cpu_interface->resetHppi(int_id);
 }
 
 void