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dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs

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ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more
than 6 bits of priority. Since this is not the case, they are currently
unimplemented.
According to spec, unimplemented registers are RAZ/WI.

Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-08-20 13:53:39 +01:00
parent 7a1f018ce7
commit 51022bfe0e
1 changed files with 55 additions and 5 deletions
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60
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -675,11 +675,35 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICH_AP0R0_EL2:
break;
// only implemented if supporting 6 or more bits of priority
case MISCREG_ICH_AP0R1:
case MISCREG_ICH_AP0R1_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP0R2:
case MISCREG_ICH_AP0R2_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP0R3:
case MISCREG_ICH_AP0R3_EL2:
// Unimplemented registers are RAZ/WI
return 0;
// Hyp Active Priorities Group 1 Registers
case MISCREG_ICH_AP1R0:
case MISCREG_ICH_AP1R0_EL2:
break;
// only implemented if supporting 6 or more bits of priority
case MISCREG_ICH_AP1R1:
case MISCREG_ICH_AP1R1_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP1R2:
case MISCREG_ICH_AP1R2_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP1R3:
case MISCREG_ICH_AP1R3_EL2:
// Unimplemented registers are RAZ/WI
return 0;
// Maintenance Interrupt State Register
case MISCREG_ICH_MISR:
case MISCREG_ICH_MISR_EL2:
@@ -1614,13 +1638,39 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
}
// Hyp Active Priorities Group 0 Registers
case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
// Hyp Active Priorities Group 1 Registers
case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
case MISCREG_ICH_AP0R0:
case MISCREG_ICH_AP0R0_EL2:
break;
// only implemented if supporting 6 or more bits of priority
case MISCREG_ICH_AP0R1:
case MISCREG_ICH_AP0R1_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP0R2:
case MISCREG_ICH_AP0R2_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP0R3:
case MISCREG_ICH_AP0R3_EL2:
// Unimplemented registers are RAZ/WI
return;
// Hyp Active Priorities Group 1 Registers
case MISCREG_ICH_AP1R0:
case MISCREG_ICH_AP1R0_EL2:
break;
// only implemented if supporting 6 or more bits of priority
case MISCREG_ICH_AP1R1:
case MISCREG_ICH_AP1R1_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP1R2:
case MISCREG_ICH_AP1R2_EL2:
// only implemented if supporting 7 or more bits of priority
case MISCREG_ICH_AP1R3:
case MISCREG_ICH_AP1R3_EL2:
// Unimplemented registers are RAZ/WI
return;
default:
panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
misc_reg, miscRegName[misc_reg]);