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dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1

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Previous mapping was wrong because it was checking which security bits
it was accessing by using the inSecureState() function, whereas it
should have used the isSecureBelowEL3().  This patch is not making the
sostitution since it is optimizing the mapping furthermore by avoiding
updating both IGRPEN1_EL1 and  IGRPEN1_EL3 on writes.  The IGRPEN1_EL1
register is used as a storage, and any reads/writes to IGRPEN1_EL3 is
routed to that register.

Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-08-21 10:08:54 +01:00
parent 5aa85f38cb
commit 54e6625546
1 changed files with 15 additions and 30 deletions
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45
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -204,8 +204,17 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
// Interrupt Group 1 Enable register EL3
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICC_IGRPEN1_EL3: {
ICC_IGRPEN1_EL3 igrp_el3 = 0;
igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
value = igrp_el3;
break;
}
// Running Priority Register
case MISCREG_ICC_RPR:
@@ -1344,23 +1353,6 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
}
if (haveEL(EL3)) {
ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
if (inSecureState()) {
// Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
} else {
// Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
}
isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
icc_igrpen1_el3);
}
setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
updateDistributor();
return;
@@ -1381,19 +1373,12 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3: {
ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
if (inSecureState()) {
// ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
} else {
// ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
}
isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
break;
isa->setMiscRegNoEffect(
MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
isa->setMiscRegNoEffect(
MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
return;
}
// Software Generated Interrupt Group 0 Register