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4988 Commits

Author SHA1 Message Date
Matthew Poremba
c028af111a arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu 
This TLB is more of an "APU" TLB than anything GCN3 specific. It can be
used with either GCN3 or Vega. With this change, VEGA_X86 builds and one
can run binaries with Vega ISA code using the same steps as GCN3 but
building the Vega ISA instead.

Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53803
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-09 17:26:15 +00:00
Matthew Poremba
85eaf9c799 arch-gcn3: Delete extraneous registers header 
This file is a duplicate of arch/amdgpu/gcn3/gpu_registers.hh and is in
the wrong location. It should be removed to avoid mistakenly editing the
wrong file.

Change-Id: Ie96e22fe8f78fda954af788b472ec2df4782e4a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-12-08 14:59:53 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject(). 
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-08 08:01:23 +00:00
Yu-hsin Wang
60e55ecef8 fastmodel: CortexR52 implements setResetAddr interface 
Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
 2021-12-08 03:12:36 +00:00
Yu-hsin Wang
0e48a05ed1 fastmodel: CortexA76 implements setResetAddr interface 
Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53327
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
 2021-12-08 03:12:36 +00:00
Yu-hsin Wang
869d225e51 fastmodel: add setResetAddr interface 
setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-08 03:12:36 +00:00
Gabe Black
7bd668217b arch-x86: Hook up the newfstatat system call for 64 bit Linux. 
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1117

Change-Id: I711fc7d7009621bb317981293725416ae74d1d3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53206
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2021-12-07 22:58:40 +00:00
Gabe Black
a8e9258f99 arch-x86: Hook up system calls for 64 bit processes. 
These system calls already exist, they just weren't hooked up yet.

Change-Id: I5c2c66d34d0286aafe686e6511948ed4a6719672
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2021-12-07 22:58:40 +00:00
Giacomo Travaglini
664fdd747a arch-arm, dev-arm: Add currEL function to the ISA class 
This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 18:58:49 +00:00
Giacomo Travaglini
2d8996a3eb arch-arm: Remove currOpMode utility function 
This was used by the currEL function only. We are progressively
removing any interface referring to Armv7 concepts

Change-Id: I1d97b392d063e85562b9234c094b1f2166e75ac9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53623
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 18:58:49 +00:00
Giacomo Travaglini
adaab745a3 arch-arm, dev-arm: Move inSecureState helper to ISA class 
The helper function should be really part of the Arm ISA class

Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53268
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 18:58:49 +00:00
Jason Lowe-Power
883b8fe826 arch-arm,arch-sparc: Remove legacy stat for faults 
This is a legacy stat that was not easy to tie to a Stats::Group.

In ARM, this stat wasn't actually counting all faults, it was only
counting the faults that occured in 32-bit mode, so it's probably safe
to remove the stat (it was wrong anyway). For SPARC, it's also unlikely
anyone is depending on this stat for their research.

Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52504
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 15:03:38 +00:00
Gabe Black
35362d15f5 arch: Delete the decoder.hh switching header file. 
Change-Id: I9340aa9fa87bcb03c27cb7107b6697ad96060dbe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52082
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
50732981ba cpu: Stop including arch/decoder.hh. 
Stop including arch/decoder.hh, and fix up transitive includes.

Change-Id: I9ef2efd0ab427e17bea4382b89a097c17e619332
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52081
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
25d36c81c9 arch,cpu: Turn the Decoder objects into SimObjects. 
Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
3e766837b0 arch,cpu: Stop using TheISA::Decoder in most places. 
The only places that still use that indirection are where the decoder
itself is instantiated with "new".

Also, add an "as" method which makes casting to an ISA specific decoder
type easier and less error prone.

Change-Id: Ib4a9cce7f96da2a9a8fe19113628694904893b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52079
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
3d52a0ea97 arch: Make the decoder decode() method virtual. 
Change-Id: I60f0c4ffbd63069caaee190a78f007df79b61808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52078
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
ce60dc8d3a arch: Make the decoder moreBytes method virtual. 
Change-Id: I9135508916de91172ec9649d59d80574ac2aaf16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52077
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
792745f4f0 arch: Make the decoder takeOverFrom method virtual. 
This is only implemented for x86. It's called very rarely, and so
virtual function overhead is practically irrelevant.

Change-Id: Ib6e05a903df95b801164e44d1662e130419fdbd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52076
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-12-06 03:09:22 +00:00
Gabe Black
b65272e7f1 arch: Remove "process()" from the Decoder interface. 
This method was only ever an implementation detail on ARM and x86, the
only places it actually did anything. Remove it from the other decoders,
and also make it protected on x86 to remove confusion.

Change-Id: I3a719648039c1edfbc2bd044f0a21c8983b249f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-03 03:24:44 +00:00
Gabe Black
81fa62fc91 arch: Make the decoder reset() method virtual. 
This is called very infrequently, and so it's virtual overhead is
practically irrelevant.

Change-Id: If92cd96f75234c65c4cdffe392c32cfdd9b0c8cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52074
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-03 03:24:44 +00:00
Gabe Black
5e7c964158 arch: Promote outOfBytes/needMoreBytes to the InstDecoder class. 
Change-Id: Ie8f31e424081f002e3d74edd1685b4a977c545c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52073
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-03 03:24:44 +00:00
Gabe Black
29950b81ce arch: Promote instReady to the base InstDecoder class. 
Move the instDone flag, and the instReady function which was
consistently implemented just to return it, to the base InstDecoder
class. This flag can still be accessed easily from the subclasses, but
now it can be retrieved with just an InstDecoder pointer without a
virtual function call.

Change-Id: I8c662aa01da8fe33ffe679071c701e0aadc1a795
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52072
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-03 03:24:44 +00:00
Gabe Black
21d7ae9508 arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs. 
Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-03 03:05:41 +00:00
Gabe Black
9fcafefe27 arch-sparc: Fix a bug in SparcNativeTrace::check. 
This method is responsible for comparing gem5's state against the state
of the real process. When checking the value of NPC, it accessed the
value of nnpc() by calling pc.nnpc(), but did not actually update regVal
with it, so the comparison was between the value from the real process
and npc().

It's mildly confusing that nnpc is compared against npc, and npc against
pc, but that's because of what the state looks like in the real process
when single stepping through it with ptrace.

You can actually see where this bug was introduced if you look at the
change which created the PCState types originally. There, you can see
how regVal was set using a method of the ThreadContext, but after that
change the value is only accessed and not actually used.

Change-Id: I0f0101db5f807640b8d25fef6448081d9cfa0213
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53363
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 23:30:06 +00:00
Gabe Black
a17eb869dc arch: Remove the pcstate.hh switching header file. 
Change-Id: I8c9cf0ec0c867b76ee8dd8f83b1d2d0835ecb3af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52068
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
2805f3dee1 misc: Stop including arch/pcstate.hh. 
Change-Id: Ic9ea62ae9c59fd838175fd6af4c075101d46a0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52067
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
7d00ef8c5b arch: Rename PCStateCommon to PCStateWithNext. 
This intermediate class has a fairly vague name. This new name more
specifically describes what this PCState class adds to its base class.

Change-Id: I6d19383f3eb2895d924187ddbf8185352db71542
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52486
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
9f2fa6c4ce arch,cpu: Make branching() a virtual member of PCStateBase. 
Change-Id: I4422d07024e97dbd67e97ad95a16e1b06fd6be12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52066
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
f8b8ab90ac arch: Make the advance() method virtual and in PCStateBase. 
It's occasionally necessary to advance the PC to the next instruction
without having an instruction to do it with. This makes it available
without having to cast to a PCState subclass.

Change-Id: I3b7d94afdfb27b34279e58158782e87ab5066a37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52065
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
b1716fb8bd arch,cpu-minor: Make the uReset method virtual in PCStateBase. 
This is used in the minor CPU, but maybe shouldn't. This makes it
accessible from a generic PCStatePtr without having to cast it to a
PCState subclass.

Change-Id: Ied89e2c9c69b1a7d647129fdade10312e21dcaa1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52064
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
Maintainer: ZHENGRONG WANG <seanyukigeek@gmail.com>
 2021-11-30 23:30:06 +00:00
Gabe Black
e75ae455ad arch,cpu: Use PCStateBase for decoder methods. 
Change-Id: I79f1c5dd39de7015a5c5b891e1888d9a176bb5b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52063
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
f315461bb7 arch,cpu: Stop using and remove ThreadContext::instAddr. 
Change-Id: I9cd8077fd72a9d7bff20f1bd7ba37e4e038b8fac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52062
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-11-30 23:30:06 +00:00
Gabe Black
9d79b751c8 cpu: Eliminate the ThreadContext::microPC method. 
This was originally intended to make it more efficient to get the
microPC without making a copy of the entire PCState object to return.
Now that the PCState is returned through a pointer without a copy and
the microPC can be accessed with an inline accessor, we don't need to
create a special accessor for it.

Change-Id: I1d354dfca6be5d954e147f23dc9d27917b379bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52061
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-11-30 23:30:06 +00:00
Gabe Black
e12120372c arch,cpu,base: Make add a virtual method to stutter the PC for KVM. 
As described in a comment in the base KVM CPU, there needs to be a way
to set the next PC of a PCState object to the actual current PC. Since
this is the only place that sort of operation is needed and it's a bit
of a hack to get around a quirk of calling pseudo instructions in a KVM
CPU, we can support it by adding a virtual method for it which is
implemented by the ISA specific subclasses of the KVM CPU.

Change-Id: Idf390e9c4ffa7398cd08e76846c61cb6da754dce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52059
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-11-30 23:30:06 +00:00
Gabe Black
8279191cd9 misc,cpu: Make ThreadContext work with PCStateBase-s. 
Change-Id: I92f1d79c697bb45f610604c9e84b24ea93d58776
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52058
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 23:30:06 +00:00
Giacomo Travaglini
29a6b75e33 arch-arm: Fix coding style in isa.hh 
Change-Id: Ib827e4ae9662e79512a18c13e1cd262213406fbf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53267
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 13:49:33 +00:00
Giacomo Travaglini
759adb78da arch-arm: Allow EL2 trapping of secure AA32 instructions 
With the introduction of FEAT_SEL2 we should allow trapping
to EL2 in secure mode. This is already implemented for AArch64
EL1. With this patch we are extending it to AArch32

Change-Id: I3551a93af7db0b1d2bdf0935c3a29e39e8db55f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53266
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 13:49:33 +00:00
Giacomo Travaglini
d937b470ad arch-arm: Fix coding style in utility.cc 
Change-Id: I46318878a9ecfacdb1b891da6064d2058774856a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53265
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 13:49:33 +00:00
Giacomo Travaglini
c52e74f971 arch-arm: Remove unused Hdcr/Hcptr operands 
Change-Id: Id20c235e765195750a18c85eb4d19cc96865ae81
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53264
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 13:49:33 +00:00
Giacomo Travaglini
cee3b6ead0 arch-arm: Use ThreadContext when trapping MCR/MRC to cop14 
We are aligning to cop15 read/writes. By passing the TC directly
we unlock the usage of TC based helper functions.

Change-Id: I1d06d31ce0bd04508f44f34cc0dcef8828d9c48c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53263
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-30 13:49:33 +00:00
Gabe Black
39584edc72 arch,cpu: Convert ExecContext::pcState to use PCStateBase. 
Some places need persistent temporaries for the return values of
ThreadContext::pcState(), which is currently by value.

Change-Id: Icd4924f1d16ebe1c99c54ed47616733422340cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52057
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-29 22:00:54 +00:00
Luming Wang
c99d192690 arch-riscv: fix inUserMode 
The original inUserMode() simply returns true. However, it should
check whether the processor's current privilege level is PRV_U.

Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53184
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-25 06:02:27 +00:00
Gabe Black
70f9a32117 cpu,arch: Eliminate the ThreadContext::nextInstAddr method. 
This is no longer used.

Change-Id: I0ec170fb3b450430bbeff0a3c37bcdafe70c92b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52053
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00
Gabe Black
58935cd5ad cpu: Stop using the ThreadContext::nextInstAddr method. 
The PCState already contains this information internally, and it can be
compared, printed, etc, implicitly alongside all the other info in the
PCState, everywhere this method was being used.

Change-Id: I30705f30a135d4ffbc3279c366dafb1184445c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52052
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-23 07:45:29 +00:00
Gabe Black
ecd3cc85f0 arch,cpu: Use PCStateBase in StaticInst::branchTarget 
Change-Id: I1b8a2ea088b52252601968b1b1083ed712a5bfd6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52045
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00
Gabe Black
9d48180e4a arch,cpu: Use PCStateBase in buildRetPC. 
Change-Id: I9d9f5b25613440737b1d67134fcae09aa68baf8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52044
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00
Gabe Black
5ad4cf0af1 arch,cpu,sim: Use PCStateBase in advancePC. 
By using a PCStateBase pointer or reference, we can (mostly) avoid
having to know what the ISA specific PState class is, letting the ISA
specific instruction classes cast to the type they need internally.

There are a couple minor places where we need to do those casts outside
of ISA specific types, one in the generic NopStaticInstPtr class, and a
few in generic faults.

Right now, we'll just use the TheISA::PCState type in those isolated
spots (sometimes hidden by auto), and deal with it later, possibly
with a virtual "advance" method of some sort.

Change-Id: I774c67dc648a85556230f601e087211b3d5630a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52043
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00
Gabe Black
cd772c1951 arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState. 
Change-Id: Ia31919ef19f973aa7af973889366412f3999342a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52042
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00
Gabe Black
f784097f7a arch: Add a "set" function to set one PCState to another. 
Most of the time, the type pointed to by a PCState pointer or reference
will be the same as all the others, if not nullptr.

This change adds a set of "set" functions which assume that the
underlying type of each pointer or reference are the same, and handles
casting, copying things over, creating a new copy, etc, for you. It uses
a new "update" virtual method on PCState subclasses which casts the
source to the same type as the destination and copies values over.

Note that the "set" function doesn't actually verify that the two types
are the same, just like the overloaded ==, != and << operators. In the
future, those checks can be added for debugging purposes, probably
guarded by a configuration variable which can be toggled on or off to
get better performance or more thorough error checking.

The main advantage of these wrappers are that they allows consistent
semantics whether your moving a value from a pointer, or from a yet
unconverted PCState subclass, or vice versa, which will be particularly
helpful while transitioning between using raw PCState instances and
using primarily pointers and references.

This change also adds wrappers which handle std::unique_ptr, which makes
it easier to use them as arguments to these functions. Otherwise, if the
std::unique_ptr is a temporary value, using the return value of .get()
will let the std::unique_ptr go out of scope, making it delete the data
pointed to by the returned pointed. By keeping the std::unique_ptr
around on the stack, that prevents it from going out of scope.

Change-Id: I2c737b08e0590a2c46e212a7b9efa543bdb81ad3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52041
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-23 07:45:29 +00:00