Giacomo Travaglini d937b470ad arch-arm: Fix coding style in utility.cc ...

Change-Id: I46318878a9ecfacdb1b891da6064d2058774856a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53265
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-11-30 13:49:33 +00:00

..

amdgpu

arch-gcn3,arch-vega: Don't write exec in v_cmp_f_i32

2021-11-05 19:52:40 +00:00

arm

arch-arm: Fix coding style in utility.cc

2021-11-30 13:49:33 +00:00

gcn3

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

generic

cpu,arch: Eliminate the ThreadContext::nextInstAddr method.

2021-11-23 07:45:29 +00:00

isa_parser

arch,cpu: Convert ExecContext::pcState to use PCStateBase.

2021-11-29 22:00:54 +00:00

mips

arch,cpu: Use PCStateBase in StaticInst::branchTarget

2021-11-23 07:45:29 +00:00

null

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

power

arch,cpu: Convert ExecContext::pcState to use PCStateBase.

2021-11-29 22:00:54 +00:00

riscv

arch,cpu: Convert ExecContext::pcState to use PCStateBase.

2021-11-29 22:00:54 +00:00

sparc

arch,cpu: Use PCStateBase in buildRetPC.

2021-11-23 07:45:29 +00:00

x86

arch,cpu: Use PCStateBase in StaticInst::branchTarget

2021-11-23 07:45:29 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

SConscript

arch: Remove the page_size.hh switching header file.

2021-10-22 21:43:02 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00