arch-arm, dev-arm: Add currEL function to the ISA class

This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.cc

@@ -629,7 +629,7 @@ ISA::readMiscReg(int misc_reg)
                   miscRegName[misc_reg]);
     }
 #endif
-    misc_reg = redirectRegVHE(tc, misc_reg);
+    misc_reg = redirectRegVHE(misc_reg);
 
     switch (unflattenMiscReg(misc_reg)) {
       case MISCREG_HCR:
@@ -1006,7 +1006,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
                     miscRegName[misc_reg], val);
         }
 #endif
-        misc_reg = redirectRegVHE(tc, misc_reg);
+        misc_reg = redirectRegVHE(misc_reg);
 
         switch (unflattenMiscReg(misc_reg)) {
           case MISCREG_CPACR:
@@ -2555,6 +2555,14 @@ ISA::inSecureState() const
     }
 }
 
+ExceptionLevel
+ISA::currEL() const
+{
+    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
+
+    return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+}
+
 unsigned
 ISA::getCurSveVecLenInBits() const
 {

src/arch/arm/isa.hh

@@ -859,10 +859,10 @@ namespace ArmISA
          * HCR_EL2.E2H is enabled and executing at EL2
          */
         int
-        redirectRegVHE(ThreadContext * tc, int misc_reg)
+        redirectRegVHE(int misc_reg)
         {
             const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
-            if (hcr.e2h == 0x0 || currEL(tc) != EL2)
+            if (hcr.e2h == 0x0 || currEL() != EL2)
                 return misc_reg;
             SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
             bool sec_el2 = scr.eel2 && release->has(ArmExtension::FEAT_SEL2);
@@ -961,6 +961,11 @@ namespace ArmISA
         /** Return true if the PE is in Secure state */
         bool inSecureState() const;
 
+        /**
+         * Returns the current Exception Level (EL) of the ISA object
+         */
+        ExceptionLevel currEL() const;
+
         unsigned getCurSveVecLenInBits() const;
 
         unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; }

src/arch/arm/pmu.cc

@@ -491,8 +491,7 @@ PMU::CounterState::isFiltered() const
     assert(pmu.isa);
 
     const PMEVTYPER_t filter(this->filter);
-    const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
-    const ExceptionLevel el(currEL(cpsr));
+    const ExceptionLevel el(pmu.isa->currEL());
     const bool secure(pmu.isa->inSecureState());
 
     switch (el) {

src/arch/arm/utility.cc

@@ -124,6 +124,13 @@ inAArch64(ThreadContext *tc)
     return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
 }
 
+ExceptionLevel
+currEL(const ThreadContext *tc)
+{
+    return static_cast<ArmISA::ISA *>(
+        const_cast<ThreadContext *>(tc)->getIsaPtr())->currEL();
+}
+
 bool
 longDescFormatInUse(ThreadContext *tc)
 {

src/arch/arm/utility.hh

@@ -108,13 +108,11 @@ bool isSecure(ThreadContext *tc);
 
 bool inAArch64(ThreadContext *tc);
 
-static inline ExceptionLevel
-currEL(const ThreadContext *tc)
-{
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-    return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
-}
+/**
+ * Returns the current Exception Level (EL) of the
+ * provided ThreadContext
+ */
+ExceptionLevel currEL(const ThreadContext *tc);
 
 inline ExceptionLevel
 currEL(CPSR cpsr)

src/dev/arm/gic_v3_cpu_interface.cc

@@ -2336,29 +2336,10 @@ Gicv3CPUInterface::inSecureState() const
     return isa->inSecureState();
 }
 
-int
+ExceptionLevel
 Gicv3CPUInterface::currEL() const
 {
-    CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
-    bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
-
-    if (is_64) {
-        return (ExceptionLevel)(uint8_t) cpsr.el;
-    } else {
-        switch (cpsr.mode) {
-          case MODE_USER:
-            return 0;
-
-          case MODE_HYP:
-            return 2;
-
-          case MODE_MON:
-            return 3;
-
-          default:
-            return 1;
-        }
-    }
+    return isa->currEL();
 }
 
 bool

src/dev/arm/gic_v3_cpu_interface.hh

@@ -309,7 +309,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
 
     void activateIRQ(uint32_t intid, Gicv3::GroupId group);
     void generateSGI(RegVal val, Gicv3::GroupId group);
-    int currEL() const;
+    ArmISA::ExceptionLevel currEL() const;
     void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
     void dropPriority(Gicv3::GroupId group);
     uint64_t eoiMaintenanceInterruptStatus() const;