fastmodel: CortexR52 implements setResetAddr interface

Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>

src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

@@ -79,6 +79,12 @@ CortexR52::setCluster(CortexR52Cluster *_cluster, int _num)
     set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
 }
 
+void
+CortexR52::setResetAddr(Addr addr, bool secure)
+{
+    evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
 Port &
 CortexR52::getPort(const std::string &if_name, PortID idx)
 {

src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

@@ -72,6 +72,8 @@ class CortexR52 : public Iris::CPU<CortexR52TC>
 
     void setCluster(CortexR52Cluster *_cluster, int _num);
 
+    void setResetAddr(Addr addr, bool secure = false) override;
+
     Port &getPort(const std::string &if_name,
             PortID idx=InvalidPortID) override;
 };

src/arch/arm/fastmodel/CortexR52/evs.cc

@@ -66,7 +66,7 @@ template <class Types>
 void
 ScxEvsCortexR52<Types>::setResetAddr(int core, Addr addr, bool secure)
 {
-    panic("Not implemented for R52.");
+    this->corePins[core]->cfgvectable.set_state(0, addr);
 }
 
 template <class Types>
@@ -78,7 +78,8 @@ ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
     amba(evs->amba[cpu], name + ".amba", -1),
     core_reset(name + ".core_reset", 0),
     poweron_reset(name + ".poweron_reset", 0),
-    halt(name + ".halt", 0)
+    halt(name + ".halt", 0),
+    cfgvectable((name + "cfgvectable").c_str())
 {
     for (int i = 0; i < Evs::PpiCount; i++) {
         ppis.emplace_back(
@@ -87,6 +88,7 @@ ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
     core_reset.signal_out.bind(evs->core_reset[cpu]);
     poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
     halt.signal_out.bind(evs->halt[cpu]);
+    cfgvectable.bind(evs->cfgvectable[cpu]);
 }
 
 

src/arch/arm/fastmodel/CortexR52/evs.hh

@@ -79,6 +79,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
     struct CorePins
     {
         using CoreInt = IntSinkPin<CorePins>;
+        template <typename T>
+        using SignalInitiator = amba_pv::signal_master_port<T>;
 
         std::string name;
         Evs *evs;
@@ -107,6 +109,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
         SignalSender core_reset;
         SignalSender poweron_reset;
         SignalSender halt;
+
+        SignalInitiator<uint64_t> cfgvectable;
     };
 
     std::vector<std::unique_ptr<CorePins>> corePins;

src/arch/arm/fastmodel/CortexR52/x1/x1.lisa

@@ -59,6 +59,9 @@ component CortexR52x1
         self.ppi_0 => core.extppi_in_0;
 
         self.spi => core.spi_in;
+
+        // Core reset addrs.
+        self.cfgvectable => core.cfgvectable;
     }
 
     properties
@@ -74,6 +77,7 @@ component CortexR52x1
     slave port<Signal> poweron_reset[1];
     slave port<Signal> halt[1];
     slave port<Signal> top_reset;
+    slave port<Value_64> cfgvectable[1];
 
     slave port<ExportedClockRateControl> clock_rate_s
     {

src/arch/arm/fastmodel/CortexR52/x2/x2.lisa

@@ -60,6 +60,9 @@ component CortexR52x2
         self.ppi_1 => core.extppi_in_1;
 
         self.spi => core.spi_in;
+
+        // Core reset addrs.
+        self.cfgvectable => core.cfgvectable;
     }
 
     properties
@@ -75,6 +78,7 @@ component CortexR52x2
     slave port<Signal> poweron_reset[2];
     slave port<Signal> halt[2];
     slave port<Signal> top_reset;
+    slave port<Value_64> cfgvectable[2];
 
     slave port<ExportedClockRateControl> clock_rate_s
     {

src/arch/arm/fastmodel/CortexR52/x3/x3.lisa

@@ -61,6 +61,9 @@ component CortexR52x3
         self.ppi_2 => core.extppi_in_2;
 
         self.spi => core.spi_in;
+
+        // Core reset addrs.
+        self.cfgvectable => core.cfgvectable;
     }
 
     properties
@@ -76,6 +79,7 @@ component CortexR52x3
     slave port<Signal> poweron_reset[3];
     slave port<Signal> halt[3];
     slave port<Signal> top_reset;
+    slave port<Value_64> cfgvectable[3];
 
     slave port<ExportedClockRateControl> clock_rate_s
     {

src/arch/arm/fastmodel/CortexR52/x4/x4.lisa

@@ -62,6 +62,9 @@ component CortexR52x4
         self.ppi_3 => core.extppi_in_3;
 
         self.spi => core.spi_in;
+
+        // Core reset addrs.
+        self.cfgvectable => core.cfgvectable;
     }
 
     properties
@@ -77,6 +80,7 @@ component CortexR52x4
     slave port<Signal> poweron_reset[4];
     slave port<Signal> halt[4];
     slave port<Signal> top_reset;
+    slave port<Value_64> cfgvectable[4];
 
     slave port<ExportedClockRateControl> clock_rate_s
     {