From 60e55ecef8310fc861e1effb0b1776c732abeacc Mon Sep 17 00:00:00 2001 From: Yu-hsin Wang Date: Mon, 29 Nov 2021 17:31:52 +0800 Subject: [PATCH] fastmodel: CortexR52 implements setResetAddr interface Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328 Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Earl Ou --- src/arch/arm/fastmodel/CortexR52/cortex_r52.cc | 6 ++++++ src/arch/arm/fastmodel/CortexR52/cortex_r52.hh | 2 ++ src/arch/arm/fastmodel/CortexR52/evs.cc | 6 ++++-- src/arch/arm/fastmodel/CortexR52/evs.hh | 4 ++++ src/arch/arm/fastmodel/CortexR52/x1/x1.lisa | 4 ++++ src/arch/arm/fastmodel/CortexR52/x2/x2.lisa | 4 ++++ src/arch/arm/fastmodel/CortexR52/x3/x3.lisa | 4 ++++ src/arch/arm/fastmodel/CortexR52/x4/x4.lisa | 4 ++++ 8 files changed, 32 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc index f5817f9ab8..85a4c2ab7a 100644 --- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc +++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc @@ -79,6 +79,12 @@ CortexR52::setCluster(CortexR52Cluster *_cluster, int _num) set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset); } +void +CortexR52::setResetAddr(Addr addr, bool secure) +{ + evs_base_cpu->setResetAddr(num, addr, secure); +} + Port & CortexR52::getPort(const std::string &if_name, PortID idx) { diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh index c43052b842..76c7d33ea4 100644 --- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh +++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh @@ -72,6 +72,8 @@ class CortexR52 : public Iris::CPU void setCluster(CortexR52Cluster *_cluster, int _num); + void setResetAddr(Addr addr, bool secure = false) override; + Port &getPort(const std::string &if_name, PortID idx=InvalidPortID) override; }; diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc index 5dcda4e7ac..720f1ccf89 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.cc +++ b/src/arch/arm/fastmodel/CortexR52/evs.cc @@ -66,7 +66,7 @@ template void ScxEvsCortexR52::setResetAddr(int core, Addr addr, bool secure) { - panic("Not implemented for R52."); + this->corePins[core]->cfgvectable.set_state(0, addr); } template @@ -78,7 +78,8 @@ ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) : amba(evs->amba[cpu], name + ".amba", -1), core_reset(name + ".core_reset", 0), poweron_reset(name + ".poweron_reset", 0), - halt(name + ".halt", 0) + halt(name + ".halt", 0), + cfgvectable((name + "cfgvectable").c_str()) { for (int i = 0; i < Evs::PpiCount; i++) { ppis.emplace_back( @@ -87,6 +88,7 @@ ScxEvsCortexR52::CorePins::CorePins(Evs *_evs, int _cpu) : core_reset.signal_out.bind(evs->core_reset[cpu]); poweron_reset.signal_out.bind(evs->poweron_reset[cpu]); halt.signal_out.bind(evs->halt[cpu]); + cfgvectable.bind(evs->cfgvectable[cpu]); } diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh index a616a4d52b..fa9d7fe6f0 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.hh +++ b/src/arch/arm/fastmodel/CortexR52/evs.hh @@ -79,6 +79,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs struct CorePins { using CoreInt = IntSinkPin; + template + using SignalInitiator = amba_pv::signal_master_port; std::string name; Evs *evs; @@ -107,6 +109,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs SignalSender core_reset; SignalSender poweron_reset; SignalSender halt; + + SignalInitiator cfgvectable; }; std::vector> corePins; diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa index a15fe74b0f..36f3279cb7 100644 --- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa @@ -59,6 +59,9 @@ component CortexR52x1 self.ppi_0 => core.extppi_in_0; self.spi => core.spi_in; + + // Core reset addrs. + self.cfgvectable => core.cfgvectable; } properties @@ -74,6 +77,7 @@ component CortexR52x1 slave port poweron_reset[1]; slave port halt[1]; slave port top_reset; + slave port cfgvectable[1]; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa index 9b992a4d37..492d289782 100644 --- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa @@ -60,6 +60,9 @@ component CortexR52x2 self.ppi_1 => core.extppi_in_1; self.spi => core.spi_in; + + // Core reset addrs. + self.cfgvectable => core.cfgvectable; } properties @@ -75,6 +78,7 @@ component CortexR52x2 slave port poweron_reset[2]; slave port halt[2]; slave port top_reset; + slave port cfgvectable[2]; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa index 18619b9a99..ed4837c369 100644 --- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa @@ -61,6 +61,9 @@ component CortexR52x3 self.ppi_2 => core.extppi_in_2; self.spi => core.spi_in; + + // Core reset addrs. + self.cfgvectable => core.cfgvectable; } properties @@ -76,6 +79,7 @@ component CortexR52x3 slave port poweron_reset[3]; slave port halt[3]; slave port top_reset; + slave port cfgvectable[3]; slave port clock_rate_s { diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa index d22079f336..73680b11cc 100644 --- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa @@ -62,6 +62,9 @@ component CortexR52x4 self.ppi_3 => core.extppi_in_3; self.spi => core.spi_in; + + // Core reset addrs. + self.cfgvectable => core.cfgvectable; } properties @@ -77,6 +80,7 @@ component CortexR52x4 slave port poweron_reset[4]; slave port halt[4]; slave port top_reset; + slave port cfgvectable[4]; slave port clock_rate_s {