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fastmodel: add setResetAddr interface

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setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2021-11-25 11:57:19 +08:00
parent 7bd668217b
commit 869d225e51
5 changed files with 25 additions and 0 deletions
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7
src/arch/arm/fastmodel/CortexA76/evs.cc
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@@ -63,6 +63,13 @@ ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
panic_if(!gem5CpuCluster, "Cluster should be of type CortexA76Cluster");
}
template <class Types>
void
ScxEvsCortexA76<Types>::setResetAddr(int core, Addr addr, bool secure)
{
panic("Not implemented for A76.");
}
template <class Types>
ScxEvsCortexA76<Types>::ScxEvsCortexA76(
const sc_core::sc_module_name &mod_name, const Params &p) :

2
src/arch/arm/fastmodel/CortexA76/evs.hh
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@@ -113,6 +113,8 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
void setResetAddr(int core, Addr addr, bool secure) override;
};
struct ScxEvsCortexA76x1Types

7
src/arch/arm/fastmodel/CortexR52/evs.cc
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@@ -62,6 +62,13 @@ ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)
panic_if(!gem5CpuCluster, "Cluster should be of type CortexR52Cluster");
}
template <class Types>
void
ScxEvsCortexR52<Types>::setResetAddr(int core, Addr addr, bool secure)
{
panic("Not implemented for R52.");
}
template <class Types>
ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
name(csprintf("%s.cpu%s", _evs->name(), _cpu)),

2
src/arch/arm/fastmodel/CortexR52/evs.hh
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@@ -156,6 +156,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
void setResetAddr(int core, Addr addr, bool secure) override;
};
struct ScxEvsCortexR52x1Types

7
src/arch/arm/fastmodel/iris/cpu.hh
View File

@@ -51,6 +51,7 @@ class BaseCpuEvs
virtual void setClkPeriod(Tick clk_period) = 0;
virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
};
// This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@ class BaseCPU : public gem5::BaseCPU
Counter totalInsts() const override;
Counter totalOps() const override { return totalInsts(); }
virtual void
setResetAddr(Addr addr, bool secure = false)
{
panic("%s not implemented.", __FUNCTION__);
}
protected:
sc_core::sc_module *evs;
// Hold casted pointer to *evs.