diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 4e0add66b0..4b25014f6b 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -63,6 +63,13 @@ ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
     panic_if(!gem5CpuCluster, "Cluster should be of type CortexA76Cluster");
 }
 
+template <class Types>
+void
+ScxEvsCortexA76<Types>::setResetAddr(int core, Addr addr, bool secure)
+{
+    panic("Not implemented for A76.");
+}
+
 template <class Types>
 ScxEvsCortexA76<Types>::ScxEvsCortexA76(
         const sc_core::sc_module_name &mod_name, const Params &p) :
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index f0e2ef5f9c..37f8363b05 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -113,6 +113,8 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
     void setSysCounterFrq(uint64_t sys_counter_frq) override;
 
     void setCluster(SimObject *cluster) override;
+
+    void setResetAddr(int core, Addr addr, bool secure) override;
 };
 
 struct ScxEvsCortexA76x1Types
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 7f992f2459..5dcda4e7ac 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -62,6 +62,13 @@ ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)
     panic_if(!gem5CpuCluster, "Cluster should be of type CortexR52Cluster");
 }
 
+template <class Types>
+void
+ScxEvsCortexR52<Types>::setResetAddr(int core, Addr addr, bool secure)
+{
+    panic("Not implemented for R52.");
+}
+
 template <class Types>
 ScxEvsCortexR52<Types>::CorePins::CorePins(Evs *_evs, int _cpu) :
         name(csprintf("%s.cpu%s", _evs->name(), _cpu)),
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index 20870dfcfb..a616a4d52b 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -156,6 +156,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
     void setSysCounterFrq(uint64_t sys_counter_frq) override;
 
     void setCluster(SimObject *cluster) override;
+
+    void setResetAddr(int core, Addr addr, bool secure) override;
 };
 
 struct ScxEvsCortexR52x1Types
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 5cb8820dac..b43eb8ecf5 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -51,6 +51,7 @@ class BaseCpuEvs
     virtual void setClkPeriod(Tick clk_period) = 0;
     virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
     virtual void setCluster(SimObject *cluster) = 0;
+    virtual void setResetAddr(int core, Addr addr, bool secure) = 0;
 };
 
 // This CPU class adds some mechanisms which help attach the gem5 and fast
@@ -86,6 +87,12 @@ class BaseCPU : public gem5::BaseCPU
     Counter totalInsts() const override;
     Counter totalOps() const override { return totalInsts(); }
 
+    virtual void
+    setResetAddr(Addr addr, bool secure = false)
+    {
+        panic("%s not implemented.", __FUNCTION__);
+    }
+
   protected:
     sc_core::sc_module *evs;
     // Hold casted pointer to *evs.