Gabe Black cd772c1951 arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState. ...

Change-Id: Ia31919ef19f973aa7af973889366412f3999342a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52042
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

2021-11-23 07:45:29 +00:00

..

amdgpu

arch-gcn3,arch-vega: Don't write exec in v_cmp_f_i32

2021-11-05 19:52:40 +00:00

arm

arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.

2021-11-23 07:45:29 +00:00

gcn3

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

generic

arch: Add a "set" function to set one PCState to another.

2021-11-23 07:45:29 +00:00

isa_parser

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

mips

arch: Add a newPCState method to the ISA class.

2021-11-23 07:45:29 +00:00

null

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

power

arch: Add a "set" function to set one PCState to another.

2021-11-23 07:45:29 +00:00

riscv

arch: Add a "set" function to set one PCState to another.

2021-11-23 07:45:29 +00:00

sparc

arch: Add a newPCState method to the ISA class.

2021-11-23 07:45:29 +00:00

x86

arch: Add a "set" function to set one PCState to another.

2021-11-23 07:45:29 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

SConscript

arch: Remove the page_size.hh switching header file.

2021-10-22 21:43:02 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00