Commit Graph

17068 Commits

Author SHA1 Message Date
Gabe Black
424eb027ff base: Add a link to documentation in the remote GDB header file.
Change-Id: I34bf4d24e58e6dfc8e8d1220a158c90fd0935e47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44608
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 04:49:33 +00:00
Gabe Black
b596aa86e2 base: Streamline the "send" method of the BaseRemoteGDB class.
The existing send method takes a const char *, but frequently the class
wants to use it to send a std::string, also frequently after generating
that string with csprintf. Rather than force each call sight to add a
.c_str() and call csprintf, this change adds helpers which will accept a
std::string and call c_str for you, or accept a format const char * and
arguments and call csprintf for you (and then call .c_str() on the
result).

Change-Id: Ifcef5e09f6469322c6040374209972528c80fb25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44607
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 04:49:14 +00:00
Gabe Black
86301ce456 cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.
There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42001
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-04-20 00:14:09 +00:00
Gabe Black
fa505b3e12 arch: Collapse unused size parameter from "as" VecPredReg method.
Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42000
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
2d95f59ece arch,cpu: Separate printing and serialization of VecPredReg.
This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
eb7d3b6b6c sim: Don't needlessly recreate ISA types in InstRecord.
The ISAs already define fully realized types. We don't need to
separately track what parameters they used and then feed them into the
same templates again elsewhere.

Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42002
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
669d2c48f2 arch,mem: Use szext instead of sext as appropriate.
When the value being passed to sext needs to be masked first, szext can
be used instead without the masking.

Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42386
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
d5c0c638c8 arch-sparc: Fix some bit manipulation bugs.
Several sext<> calls had an off by one sign bit index, which is really
the size of the number which is being sign extended. Also, two calls in
arch/sparc/tlb.cc seemed to assume that the argument to that function
was modified in place, where really the new value is returned
separately. Move the call to sext so its return value is used and not
thrown away.

Change-Id: I86cb81ad243558e1a0d33def7f3eebe6973d6800
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
dff67336fb arch-sparc: Wrap overly long lines in the decoder definition.
Change-Id: I194f4367bd889fa6639046675b2f565a4e03bc4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42383
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
2f78ad6f7b base: Improve handling of thread IDs for remote GDB.
The remote GDB protocol encode thread IDs as positive integers, where 0
is a special value which indicates "pick any thread", and -1 is a
special value which indicates all threads.

The previous implementation would look like it worked handling the
special value -1 (for instance) because it see the '-' of "-1", stop
looking for digits, and return the default value 0.

This new implementation handles -1 as a special case, and will report an
error if no digits were found otherwise.

Also this change adds an encodeThreadId method to convert a ContextID
into a GDB thread ID by adding one to avoid the special value 0.

Change-Id: Iec54fbd9563d20a56011f48d50d69111ed1467b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44606
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:11:19 +00:00
Gabe Black
7e85c8b712 sim: Minor cleanup of the System class.
Fix style, move constant initialization out of the constructor and into
the class body, and minorly streamline an if condition.

Change-Id: I8ef42dcb8336ece58578cbd1f33937103b42989f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44605
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:11:19 +00:00
Daniel R. Carvalho
dca020e98c scons: Allow declaring dependencies of tags
It was quite incovenient to declare tags. tags either
had to be added to the Source declaration of included
files, or using (with_tag()) would need to be added
with all the indirect sub-tags. For example,

Assume:
- B.cc refers to symbols in A.cc
- C.cc refers to symbols in B.cc (i.e., it needs A transitively)
- D.cc refers to symbols in A.cc and C.cc (i.e., it needs B trans.)

So either their SConscript would be:
  Source('A.cc', add_tags=['B', 'D'])
  Source('B.cc', add_tags='B')
  Source('C.cc', add_tags='C')
  Source('D.cc', add_tags='D')

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_any_tags('B', 'C'))
  GTest('D.test', 'D.test.cc', with_any_tags('B', 'C', 'D'))

or:
  Source('A.cc', add_tags=['B', 'C', 'D'])
  Source('B.cc', add_tags=['B', 'C', 'D'])
  Source('C.cc', add_tags=['C', 'D'])
  Source('D.cc', add_tags='D')

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_tag('C'))
  GTest('D.test', 'D.test.cc', with_tag('D'))

This change makes it simpler. The tag should be added
only to the files directly included by the functionality
being tagged. Using the same example:

  Source('A.cc', add_tags=['B', 'D'])
  Source('B.cc', add_tags='B')
  Source('C.cc', add_tags='C')
  Source('D.cc', add_tags='D')

  env.TagImplies('B', 'A')
  env.TagImplies('C', 'B')
  env.TagImplies('D', ['A', 'C'])

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_tag('C'))
  GTest('D.test', 'D.test.cc', with_tag('D'))

This also means that when a file no longer refers to
symbols from other file, or when it starts refering to
symbols from another file, one only needs to change
the dependencies of the tag directly being modified,
not the tags that rely on (imply) them. That is, on
the previous example, if C stops refering to symbols
from B, then tags that imply C do not need to be
modified:

  env.TagImplies('B','A')
  env.TagImplies('D', ['A', 'C'])

Change-Id: I5be07b01864f8d5df83f59002dfd2f01c73d5e09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43587
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 13:44:11 +00:00
Giacomo Travaglini
fe3c2cd8a7 util: Remove unused package import
Change-Id: I67a03cffad11d4b26a193cc2c5ccb4cd30159a48
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Giacomo Travaglini
8f3e00d630 util: Fix cpt_upgrader format string
Change-Id: I9d15316f199b20976420c35d2c79dd13cc9db9ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44510
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Giacomo Travaglini
31c9813695 configs: Remove Ruby on ARM warning
The warning was discouraging using Ruby on ARM

Change-Id: I7ccb44cdc1d32ff1258f09bc4d0d4892a758a6ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44509
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Yu-hsin Wang
e0ef7518c2 systemc: Extend TlmBridges to 512 bits
Change-Id: I41763743974665e78ff05203d6ad2b8ac14ad625
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44528
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 03:09:18 +00:00
Gabe Black
e035575ea0 scons: Move MakeAction into gem5_scons.
That will make it usable from builders defined outside of SConstruct.

Change-Id: Id1231a1a370b7d519a382db892ded93c604eb56f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40968
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-04-18 02:32:45 +00:00
Gabe Black
6ca6f41052 scons: Move the "duplicate" setting into gem5_env_defaults.py.
This is a generic default environment setting, and so should go
alongside all the other generic default environment settings.

Change-Id: If3032a4893dd84f7c7d77e7e9420436ab445cf2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-18 02:32:45 +00:00
Gabe Black
789b6eb615 scons: Stop piggy-backing on the default tool for default settings.
Instead, create a new tool called EnvDefaults. This tool now needs
to be explicitly listed in the set of tools available through an
Environment, but that's easy to do in on place (all environments should
stem from main). Hijacking default like we were doing was (as far as I
can tell) not how that tool was intended to be used, and doing things
this way is a bit less hacky.

Also, we can split more Builders, etc, out of SConstruct, and these will
need to attach to main in the same way. We're going to need a list of
tools when main is constructed one way or the other, so we might as well
follow the rules.

Change-Id: I392e1639cb69d373c64970dccf45258000498cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40965
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-17 22:41:07 +00:00
Gabe Black
14f14f9a62 arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.

Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 22:39:37 +00:00
Gabe Black
96229439e6 arch-power: Fix power build.
Change-Id: I38b1d9e4360a8eb1cfc80bee369b5aa503dd6db2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44585
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-04-17 13:27:11 +00:00
Gabe Black
3bd72b42d0 cpu: De-templatize the BaseO3DynInst.
Change-Id: If77561b811e10adf54a8b9e28f61e143ed3ead33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42096
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 08:39:49 +00:00
Gabe Black
f484341215 cpu: Get rid of the unused eaSrcsReady method.
This method wasn't used by anything, and also made very unsafe
assumptions about what different source registers were used for.

Change-Id: I8f58aa70e139d3895499e04c86d8de2530e17d5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42095
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:41 +00:00
Gabe Black
1daf4bf39d cpu: Merge the BaseDynInst and the BaseO3DynInst classes.
Despite the generic sounding name and sort of generic contents, the
BaseDynInst was actually tied to the O3 CPU. Having the two independent
moving pieces created complexity but provided no real benefit. This was
evidenced by the fact that no CPU other than O3 actually used that
class.

Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 01:33:13 +00:00
Giacomo Travaglini
55498f45dd arch-arm: Move TLB stats update within the lookup method
This is preparing for getTE becoming a MMU method: we still want
those stats to be part of the TLB class as they are TLB related

Change-Id: I7078385fd150144dc5dd4924961e4eaaa7e2446a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35245
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-16 13:12:46 +00:00
Giacomo Travaglini
fe579ef08c tests: Use MatchFileRegex vierifier for realview regressions
We have seen cases where the primary CPU was not able to bootstrap the
secondary CPUs in multicore tests (dual). The Linux booting process
"quietly" gives up (no panic) and it completes the booting without
bringing up the seondary CPU(s). This makes the dual test useless as it
is supposed to test SMP setups.

By adding a MatchFileRegex verifier, we make sure we are able to catch
these cases, correctly raising an error if not all CPUs are available.
We do this by inspecting the kernel log for the following print:

"CPU1: Booted secondary processor"

There are probably more resilient alternatives to a regex based check,
but those require a less minimal rootfs (the current
m5_exit.squashfs.arm64 FS has a single /sbin/init binary executing a
simple m5 exit operation)

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I37e0882967443449d5fedfe3963bd25528a030f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44446
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-04-16 10:12:53 +00:00
Giacomo Travaglini
eff396359f tests: Arm FS regressions using new guest binaries
The aarch-system-20210904.tar.bz2 tarball has been added to reflect
changes in the bootloader

Change-Id: I5c93b92d15a0d2c9ef53ab9e25d44e6154af8fd6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44345
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2021-04-16 10:12:21 +00:00
Giacomo Travaglini
c2b91143b4 dev-arm: Turn flash1 into a CFI Flash Memory
Change-Id: I21bdc165fba88d6366ea500a8a662fe0dcc02dab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41496
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-16 09:52:55 +00:00
Giacomo Travaglini
5a23c6e0ce mem: CFI Flash Memory implementation
CfiMemory: This is modelling a flash memory adhering to the
Common Flash Interface (CFI):

JEDEC JESD68.01
JEDEC JEP137B
Intel Application Note 646

This is as of now a pure functional model of a flash controller: no
timing/power information has been encoded in it and it is therefore not
representive of a real device. Some voltage/timing values have
nevertheless been encoded in the CFI table.  This is just a requirement
from the CFI specification: guest software might query those entries,
but they are not reflected in gem5 statistics.

The model is meant to be used to allow execution of flash drivers (e.g.
UEFI firmware storing EFI variables in non volatile memory)

JIRA: https://gem5.atlassian.net/browse/GEM5-913

Change-Id: Id99e331ac8237f3ecb69d618da0d7ca7b038cd1f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41495
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-16 09:52:55 +00:00
Sandipan Das
e9b68ed6ac arch-power: Use 64-bit registers and operands
This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with recent versions of the Power ISA. This
allows the registers to be used for both 32-bit and 64-bit
execution modes.

It should be noted that in 32-bit mode, the use of upper
word is dependent on the instruction being executed and in
some cases, this may be undefined.

Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40881
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-16 05:52:57 +00:00
Sandipan Das
bd7b00bd24 arch-power: Refactor CR field generation
This splits the existing makeCRField utility into signed
and unsigned variants to help callers avoid confusion.
The CR bit union is also used to clean up the underlying
bit setting logic.

Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42943
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-16 05:36:27 +00:00
Michael LeBeane
a5f55e0be1 gpu-compute: Topology and driver changes for dGPU
New topology ripped from Fiji to support dGPU.  A dGPU flag is added to
the config which is propogated to the driver.  The emulated driver is
now able to properly deal with dGPU ioctls and mmaps.  For now, dGPU
physical memory is allocated from the host, but this is easy to change
once we get a GPU memory controller up and running.

Change-Id: I594418482b12ec8fb2e4018d8d0371d56f4f51c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42214
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 16:41:11 +00:00
Giacomo Travaglini
dabb0c8f45 misc: Replace std::conditional with std::conditional_t
Change-Id: I50d26d958d521c30b69d31426380b1e2e213a9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44506
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 08:15:45 +00:00
Giacomo Travaglini
8e5e603041 misc: Fix VecPredReg coding style
* get_bits -> getBits
* set_bits -> setBits
* set_raw -> setRaw
* get_raw -> getRaw

Change-Id: I57c0217dc399b7e1c5b007ed862d7ed221d5ac0b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44505
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 08:15:45 +00:00
Giacomo Travaglini
921d370135 dev: Fix GCN3_X86 builds on aarch64 host
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ic826f0cb46e07b9b5135eee1e518bc13f3d978a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44485
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 08:02:45 +00:00
handsomeliu
490b41eaac cpu: Increased the upper bound of cpu issue width
The upper bound was 8, but issue width increased to 12 since Cortex A77.
(https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a77)
This CL increased the upper bound to 12.

Bug: 175759373
Test: gem5/main/config/example/se.py
Change-Id: I9d084b940628a2bcfa676d386d3d1a82ba9b03f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44225
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 07:55:54 +00:00
Srikant Bharadwaj
6fa7e50d66 mem-garnet: Enable bridge rescheduling for DVFS
The Bridge SimObject, which hosts the CDC and SerDes functionality,
could be woken up out-of-order when changing frequencies in DVFS.
This change ensures there is no packet drop during the transition
times.

Change-Id: I40240dcb3e957217abd2d7ad22cc4f78809f7b49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44287
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
Srikant Bharadwaj
ef96d4cc5c mem-garnet: Change flitbuffer structure to deque
Flitbuffers act as FIFOs for internal links and output queues
in routers. This change replaces the use of vectors with deque
for performance improvements. The older implementation of using
a vector combined with a heap sort was both incorrect and
inefficient.

Incorrect because flit buffers should act strictly
as FIFO, sorting them based on time changes the order which affects
functionality in the case of DVFS enabled NoCs.

Change-Id: Ieba40f85628b7c7255e86792d40b8ce3d7ac34b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44286
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
Srikant Bharadwaj
40c69e8f64 mem-garnet: Reduce complexity of data structures within SwitchAllocator
The switch allocator implements a two step separable allocator and
utilizes port winner and vc winner data structures for functionality.
This improves the data structures used and their operations to improve
overall performance of the simulation. We start with an invalid output
port(-1) and an invalid vc(-1) and then allocate the outports
and vcs to inport.

Change-Id: I38b70ebdc1a54b8f748c2a5d510814bf139b9eaa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
Jui-min Lee
c4aad44a62 systemc: Fix tlm phase ordering in Gem5ToTlmBridge
Previously we only rely on timestamp to schedule all phase change events
of tlm transactions in Gem5ToTlmBridge. However, it is valid to have
END_REQ and BEGIN_RESP of a transaction to be scheduled at the same
timestamp and the gem5 scheduler will not necessary order them in a
correct way.

This unfortunately breaks the code as sending a response before
accepting a request doesn't make sense at all and will trigger an
assertion failure.

In this CL we slightly increase the priority of END_REQ event so we can
always process phase change events in a correct order.

Change-Id: Ic33a92162c8c53af3887c7b04090115a38f96866
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44305
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 16:46:59 +00:00
Giacomo Travaglini
d1e090eec4 arch-arm: Make TLB misses from a sw prefetch visible
While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.

This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss

Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 15:50:22 +00:00
Daniel R. Carvalho
e7e03df9a9 cpu-o3: Fix missing overrides
Fix missing overrides in SimpleTrace.

Change-Id: I82ed2a10c98ea67dde7b99db13c0ad5d9ed96f0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44405
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 00:09:06 +00:00
Hoa Nguyen
f8d8547575 util: Add missing parameter for print_insts
JIRA: https://gem5.atlassian.net/browse/GEM5-949

Change-Id: I74fe7adc06124d193f17d682882766484ac18528
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44448
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:40:10 +00:00
Hoa Nguyen
004692487f util: Make o3-pipeview Python3 compatible
JIRA: https://gem5.atlassian.net/browse/GEM5-955

Change-Id: I48cb0bfb784eafe2057eb1095e6aad7abf9a1bc9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44447
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:40:03 +00:00
Giacomo Travaglini
12fa117ed2 tests: Define a MatchFileRegex verifier
Using it as a base class for MatchRegex.
While the latter is using a regex to scan the stdout and stderr files,
MatchFileRegex is more generically allowing you to specify which file to
scan at __init__ time.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I2a64dab9c88a632b0a6b400ba02aafe473b3e62d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44445
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:01:17 +00:00
Yu-hsin Wang
7f91f4726a systemc: Eliminate ClockTick duplicated name warning
In systemc, a module name is consist of hierarchy names with dot
separated. The basename is the last part of the module name. Because
lack of hierarchy information, it's a chance that the basename is
duplicated. Although, ClockTick is using sc_gen_unique_name to solve
this, the warning from sc_gen_unique_name is annoying. To solve this
completely, we should use the full module name to construct the name of
ClockTick.

Change-Id: Ie664fe4757a05f72860be49c3a9d1172f824eb2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44425
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 07:39:35 +00:00
Yu-hsin Wang
2cbf4170c9 systemc: Fix verify.py and make it python 3 compatible
1. The logger behavior change breaks verify.py.
commit 8deb205ea1
Author: Daniel Carvalho <odanrc@yahoo.com.br>
Date:   Wed Mar 3 16:49:05 2021 -0300

    base: Add LOC to Loggers

    Printing the line and the file that triggered a log
    is useful for debugging.

    Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
    Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
    Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
    Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Tested-by: kokoro <noreply+kokoro@google.com>

2. Use bytes diff in LogChecker.
In Python3, string is required to be in a certain encoding, while in Python2,
it is not. In the testcase, misc/cae_test/general/bitwise/or/datatypes,
it contains some invalid codepoint of utf-8, we need diff the log with
bytes in Pyhton3.

3. Python3 compatible.
* dict.iteritems -> dict.items
* remove object base class
* use `except as` when catching exceptions
* handle map and filter behavior change

Test with

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt --phase verify --result-file

Change-Id: Ibf5b99d08a948387cf6162c476c294c49a7dac0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44465
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 07:39:35 +00:00
Gabe Black
c2f71c71d2 scons,systemc: In clang <= 6, -Wno-self-assign-overloaded doesn't exist.
In those versions of clang, use -Wno-self-assign.

Change-Id: Ic4f2fba6881f65fd40d0a4f3d3fb76574614b29a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44385
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-13 01:05:03 +00:00
Gabe Black
960b9246c5 scons: Convert gem5_scons.Configure to a context manager.
This has two purposes. First, SCons assumes that once you call
Configure, you won't set up the environment the Configure is based on
until after you get the environment back from it again with
conf.Finish(). We get away with this when the cache mode for config
tests is not "force", since Configure just reuses the environment we
pass in, and any changes we make are immediately communicated between
the two.

If the cache mode *is* "force" though, SCons modifies the decider so
that everything the conf environment goes to build looks like it's out
of date. It does that by cloning the original environment, and then
using that clone to do its tests. That causes a problem because we have
a long lived "conf" object and make further changes to main, and since
the two environments are now separate the one in conf doesn't see those
updates.

Second, and more subtly, we export our "main" and "env" environments so
that other SConsopts and SConscript files can use them and define things
in them. The way Configure is designed, if the config caching mode is
"force", then it will create a new environment, and then that
environment will replace what the, for instance, "main" variable points
to when "main = conf.Finish()" is executed.

Unfortunately, if we've already Export()-ed main, we've exported what
the "main" variable pointed to at that time. Our view of "main" will
track with the value that conf.Finish() returned, but since that
construction environment is mearly derived from the main we Exported and
not actually the same thing, they have diverged at that point and will
behave independently.

To solve both of these problems, this change modifies the
gem5_scons.Configure() method so that it's a context manager instead of
a regular function. As before, it will call Configure for us and create
a configuration context, which it will yield as the "with" value. When
the context exits, all the variables in the context Finish() returns
will be shoved back into the original context with Replace(). This isn't
perfect since variables which were deleted in the environment (probably
very rare in practice) will not exist and so will not overwrite the
still existent variable in the original dict.

This has several advantages. The environment never splits into two
copies which continue on independently. It makes the lifetime of a
configuration context short, which is good because behavior during that
time is tricky and unintuitive. It also makes the scope of the context
very clear, so that you won't miss the fact that you're in a special
setting and need to pay attention to what environment you're modifying.

Also, this keeps the conceptual overhead of configuration localized to
where the configuration is happening. In parts of the SConscripts which
are not doing anything with conf, etc, they don't have to modify their
behavior since no configuration context is active.

This change is based on this change from Hanhwi Jang who identified this
problem and proposed an initial solution:

https://gem5-review.googlesource.com/c/public/gem5/+/44265

Change-Id: Iae0a292d6b375c5da98619f31392ca1de6216fcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44389
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Hanhwi Jang <jang.hanhwi@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 01:04:54 +00:00
Giacomo Travaglini
7c2140f576 tests: Add realview-kvm-dual regression
This is to test multiple KVM vCPUs

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ied4f578bcf8d30f9c1738aa1c4265220e78589e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44326
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 13:13:17 +00:00