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arch-power: Refactor CR field generation

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This splits the existing makeCRField utility into signed
and unsigned variants to help callers avoid confusion.
The CR bit union is also used to clean up the underlying
bit setting logic.

Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42943
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Sandipan Das
2021-02-14 13:21:02 +05:30
committed by Boris Shingarov
parent a5f55e0be1
commit bd7b00bd24
3 changed files with 21 additions and 19 deletions
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30
src/arch/power/insts/integer.hh
View File

@@ -65,28 +65,30 @@ class IntOp : public PowerStaticInst
/* Compute the CR (condition register) field using signed comparison */
inline uint32_t
makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
makeCRFieldSigned(int64_t a, int64_t b, bool so) const
{
uint32_t c = xerSO;
Cr cr = 0;
/* We've pre-shifted the immediate values here */
if (a < b) { c += 0x8; }
else if (a > b) { c += 0x4; }
else { c += 0x2; }
return c;
if (a < b) { cr.cr0.lt = 1; }
else if (a > b) { cr.cr0.gt = 1; }
else { cr.cr0.eq = 1; }
if (so) { cr.cr0.so = 1; }
return cr.cr0;
}
/* Compute the CR (condition register) field using unsigned comparison */
inline uint32_t
makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
makeCRFieldUnsigned(uint64_t a, uint64_t b, bool so) const
{
uint32_t c = xerSO;
Cr cr = 0;
/* We've pre-shifted the immediate values here */
if (a < b) { c += 0x8; }
else if (a > b) { c += 0x4; }
else { c += 0x2; }
return c;
if (a < b) { cr.cr0.lt = 1; }
else if (a > b) { cr.cr0.gt = 1; }
else { cr.cr0.eq = 1; }
if (so) { cr.cr0.so = 1; }
return cr.cr0;
}
std::string generateDisassembly(

8
src/arch/power/isa/decoder.isa
View File

@@ -39,12 +39,12 @@ decode OPCODE default Unknown::unknown() {
format IntImmOp {
10: cmpli({{
Xer xer = XER;
uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
11: cmpi({{
Xer xer = XER;
uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
}
@@ -250,12 +250,12 @@ decode OPCODE default Unknown::unknown() {
format IntOp {
0: cmp({{
Xer xer = XER;
uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
32: cmpl({{
Xer xer = XER;
uint32_t cr = makeCRField(Ra, Rb, xer.so);
uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
144: mtcrf({{

2
src/arch/power/isa/formats/integer.isa
View File

@@ -77,7 +77,7 @@ setXERCode = 'XER = xer;'
computeCR0Code = '''
Cr cr = CR;
cr.cr0 = makeCRField((int32_t)%(result)s, (int32_t)0, xer.so);
cr.cr0 = makeCRFieldSigned(%(result)s, 0, xer.so);
CR = cr;
'''