derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch,mem: Use szext instead of sext as appropriate.

Browse Source 
When the value being passed to sext needs to be masked first, szext can
be used instead without the masking.

Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42386
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-03-07 00:10:23 -08:00
parent d5c0c638c8
commit 669d2c48f2
11 changed files with 31 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/arch/amdgpu/gcn3/insts/instructions.cc
View File

@@ -5728,8 +5728,7 @@ namespace Gcn3ISA
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
* sext<24>(bits(src1[lane], 23, 0));
vdst[lane] = szext<24>(src0[lane]) * szext<24>(src1[lane]);
}
}
@@ -5760,10 +5759,8 @@ namespace Gcn3ISA
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
VecElemI64 tmp_src0
= (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
VecElemI64 tmp_src1
= (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
VecElemI64 tmp_src0 = (VecElemI64)szext<24>(src0[lane]);
VecElemI64 tmp_src1 = (VecElemI64)szext<24>(src1[lane]);
vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
}
@@ -23563,8 +23560,7 @@ namespace Gcn3ISA
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
* sext<24>(bits(src1[lane], 23, 0));
vdst[lane] = szext<24>(src0[lane]) * szext<24>(src1[lane]);
}
}
@@ -23605,10 +23601,8 @@ namespace Gcn3ISA
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
VecElemI64 tmp_src0
= (VecElemI64)sext<24>(bits(src0[lane], 23, 0));
VecElemI64 tmp_src1
= (VecElemI64)sext<24>(bits(src1[lane], 23, 0));
VecElemI64 tmp_src0 = (VecElemI64)szext<24>(src0[lane]);
VecElemI64 tmp_src1 = (VecElemI64)szext<24>(src1[lane]);
vdst[lane] = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
}
@@ -27785,8 +27779,8 @@ namespace Gcn3ISA
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
vdst[lane] = sext<24>(bits(src0[lane], 23, 0))
* sext<24>(bits(src1[lane], 23, 0)) + src2[lane];
vdst[lane] = szext<24>(src0[lane])
* szext<24>(src1[lane]) + src2[lane];
}
}

8
src/arch/arm/insts/vfp.cc
View File

@@ -692,9 +692,9 @@ vfpSFixedToFpS(bool flush, bool defaultNan,
{
fesetround(FeRoundNearest);
if (width == 16)
val = sext<16>(val & mask(16));
val = szext<16>(val);
else if (width == 32)
val = sext<32>(val & mask(32));
val = szext<32>(val);
else if (width != 64)
panic("Unsupported width %d", width);
@@ -731,9 +731,9 @@ vfpSFixedToFpD(bool flush, bool defaultNan,
{
fesetround(FeRoundNearest);
if (width == 16)
val = sext<16>(val & mask(16));
val = szext<16>(val);
else if (width == 32)
val = sext<32>(val & mask(32));
val = szext<32>(val);
else if (width != 64)
panic("Unsupported width %d", width);

7
src/arch/mips/isa/decoder.isa
View File

@@ -2445,12 +2445,11 @@ decode OPCODE_HI default Unknown::unknown() {
}
}});
0x3: shilov({{
if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) {
if ((int64_t)szext<6>(Rs_sw) < 0) {
dspac = (uint64_t)dspac <<
-sext<6>(Rs_sw<5:0>);
-sext<6>(Rs_sw);
} else {
dspac = (uint64_t)dspac >>
sext<6>(Rs_sw<5:0>);
dspac = (uint64_t)dspac >> szext<6>(Rs_sw);
}
}});
0x7: mthlip({{

2
src/arch/sparc/insts/blockmem.hh
View File

@@ -75,7 +75,7 @@ class BlockMemImmMicro : public BlockMemMicro
BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, int8_t _offset) :
BlockMemMicro(mnem, _machInst, __opClass, _offset),
imm(sext<13>(bits(_machInst, 12, 0)))
imm(szext<13>(_machInst))
{}
std::string generateDisassembly(

6
src/arch/sparc/insts/branch.hh
View File

@@ -77,8 +77,7 @@ class BranchNBits : public BranchDisp
protected:
// Constructor
BranchNBits(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass,
sext<bits + 2>((_machInst & mask(bits)) << 2))
BranchDisp(mnem, _machInst, __opClass, szext<bits>(_machInst) << 2)
{}
};
@@ -105,8 +104,7 @@ class BranchImm13 : public Branch
protected:
// Constructor
BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
Branch(mnem, _machInst, __opClass),
imm(sext<13>(bits(_machInst, 12, 0)))
Branch(mnem, _machInst, __opClass), imm(szext<13>(_machInst))
{}
std::string generateDisassembly(

6
src/arch/sparc/insts/integer.hh
View File

@@ -83,7 +83,7 @@ class IntOpImm10 : public IntOpImm
protected:
// Constructor
IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass, sext<10>(bits(_machInst, 9, 0)))
IntOpImm(mnem, _machInst, __opClass, szext<10>(_machInst))
{}
};
@@ -94,7 +94,7 @@ class IntOpImm11 : public IntOpImm
{
protected:
IntOpImm11(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass, sext<11>(bits(_machInst, 10, 0)))
IntOpImm(mnem, _machInst, __opClass, szext<11>(_machInst))
{}
};
@@ -105,7 +105,7 @@ class IntOpImm13 : public IntOpImm
{
protected:
IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass, sext<13>(bits(_machInst, 12, 0)))
IntOpImm(mnem, _machInst, __opClass, szext<13>(_machInst))
{}
};

2
src/arch/sparc/insts/mem.hh
View File

@@ -60,7 +60,7 @@ class MemImm : public Mem
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
Mem(mnem, _machInst, __opClass), imm(sext<13>(bits(_machInst, 12, 0)))
Mem(mnem, _machInst, __opClass), imm(szext<13>(_machInst))
{}
std::string generateDisassembly(

5
src/arch/sparc/isa/decoder.isa
View File

@@ -155,7 +155,7 @@ decode OP default Unknown::unknown()
Y = Rd<63:32>;
}});
0x0B: smul({{
Rd_sdw = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
Rd_sdw = szext<32>(Rs1_sdw) * szext<32>(Rs2_or_imm13);
Y = Rd_sdw<63:32>;
}});
0x0C: subc({{Rd_sdw = Rs1_sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
@@ -215,8 +215,7 @@ decode OP default Unknown::unknown()
Y = resTemp<63:32>;}});
0x1B: IntOpCcRes::smulcc({{
int64_t resTemp;
Rd = resTemp = sext<32>(Rs1_sdw<31:0>) *
sext<32>(Rs2_or_imm13<31:0>);
Rd = resTemp = szext<32>(Rs1_sdw) * szext<32>(Rs2_or_imm13);
Y = resTemp<63:32>;}});
0x1C: subccc({{
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;

4
src/arch/sparc/tlb.cc
View File

@@ -1238,7 +1238,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
itb->sfsr = data;
break;
case 0x30:
itb->tag_access = sext<60>(bits(data, 59,0));
itb->tag_access = szext<60>(data);
break;
default:
goto doMmuWriteError;
@@ -1314,7 +1314,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
sfsr = data;
break;
case 0x30:
tag_access = sext<60>(bits(data, 59,0));
tag_access = szext<60>(data);
break;
case 0x80:
tc->setMiscReg(MISCREG_MMU_PART_ID, data);

2
src/mem/cache/compressors/dictionary_compressor.hh vendored
View File

@@ -776,7 +776,7 @@ class DictionaryCompressor<T>::SignExtendedPattern
const DictionaryEntry& dict_bytes, const int match_location)
{
const T data = DictionaryCompressor<T>::fromDictionaryEntry(bytes);
return data == sext<N>(data & mask(N));
return data == (T)szext<N>(data);
}
DictionaryEntry

8
src/mem/cache/compressors/fpc.hh vendored
View File

@@ -266,16 +266,16 @@ class FPC::SignExtendedTwoHalfwords : public Pattern
int16_t(data & mask(16)),
int16_t((data >> 16) & mask(16))
};
return (halfwords[0] == sext<8>(halfwords[0] & mask(8))) &&
(halfwords[1] == sext<8>(halfwords[1] & mask(8)));
return (halfwords[0] == (uint16_t)szext<8>(halfwords[0])) &&
(halfwords[1] == (uint16_t)szext<8>(halfwords[1]));
}
DictionaryEntry
decompress(const DictionaryEntry dict_bytes) const override
{
uint16_t halfwords[2] = {
uint16_t(sext<8>(extendedBytes[0]) & mask(16)),
uint16_t(sext<8>(extendedBytes[1]) & mask(16))
(uint16_t)szext<8>(extendedBytes[0]),
(uint16_t)szext<8>(extendedBytes[1])
};
return toDictionaryEntry((halfwords[1] << 16) | halfwords[0]);
}