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arch-sparc: Fix some bit manipulation bugs.

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Several sext<> calls had an off by one sign bit index, which is really
the size of the number which is being sign extended. Also, two calls in
arch/sparc/tlb.cc seemed to assume that the argument to that function
was modified in place, where really the new value is returned
separately. Move the call to sext so its return value is used and not
thrown away.

Change-Id: I86cb81ad243558e1a0d33def7f3eebe6973d6800
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-03-09 02:07:45 -08:00
parent dff67336fb
commit d5c0c638c8
2 changed files with 3 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/sparc/insts/integer.hh
View File

@@ -94,7 +94,7 @@ class IntOpImm11 : public IntOpImm
{
protected:
IntOpImm11(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass, sext<10>(bits(_machInst, 10, 0)))
IntOpImm(mnem, _machInst, __opClass, sext<11>(bits(_machInst, 10, 0)))
{}
};

6
src/arch/sparc/tlb.cc
View File

@@ -1238,8 +1238,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
itb->sfsr = data;
break;
case 0x30:
sext<59>(bits(data, 59,0));
itb->tag_access = data;
itb->tag_access = sext<60>(bits(data, 59,0));
break;
default:
goto doMmuWriteError;
@@ -1315,8 +1314,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
sfsr = data;
break;
case 0x30:
sext<59>(bits(data, 59,0));
tag_access = data;
tag_access = sext<60>(bits(data, 59,0));
break;
case 0x80:
tc->setMiscReg(MISCREG_MMU_PART_ID, data);