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arch-power: Use 64-bit registers and operands

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This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with recent versions of the Power ISA. This
allows the registers to be used for both 32-bit and 64-bit
execution modes.

It should be noted that in 32-bit mode, the use of upper
word is dependent on the instruction being executed and in
some cases, this may be undefined.

Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40881
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Sandipan Das
2021-02-06 17:12:32 +05:30
committed by Boris Shingarov
parent bd7b00bd24
commit e9b68ed6ac
1 changed files with 10 additions and 10 deletions
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20
src/arch/power/isa/operands.isa
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@@ -41,10 +41,10 @@ def operand_types {{
def operands {{
# General Purpose Integer Reg Operands
'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
@@ -54,16 +54,16 @@ def operands {{
'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
# Memory Operand
'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),
# Program counter and next
'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
# Control registers
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
# Setting as IntReg so things are stored as an integer, not double
@@ -72,5 +72,5 @@ def operands {{
# Registers for linked loads and stores
'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
}};