The --restore_simpoint_checkpoint option is a boolean;
however if no default value is supplied, optparse sets the
default value to None
This is not valid for argparse. Argparse recognizes the store_true
action and it is automatically treating the option as a boolean,
hence providing a default=False instead of default=None
Change-Id: I6b09edf6911be71a06001730be1232a1b5c8482c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44765
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The code which registers thread contexts originally returned the ID that
it had chosen, and let the CPU actually set the ID in the object itself.
That opened a window where calling contextId() on the ThreadContext
would return the wrong answer.
Instead, we can just set the ID immediately after it's decided. This
also localizes that logic and removes plumbing for the ID between that
decision and where it's actually applied.
Change-Id: I31ad84c3f9bf6f5b6f72457ca640ea929b24f6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44615
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
The existing send method takes a const char *, but frequently the class
wants to use it to send a std::string, also frequently after generating
that string with csprintf. Rather than force each call sight to add a
.c_str() and call csprintf, this change adds helpers which will accept a
std::string and call c_str for you, or accept a format const char * and
arguments and call csprintf for you (and then call .c_str() on the
result).
Change-Id: Ifcef5e09f6469322c6040374209972528c80fb25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44607
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Several sext<> calls had an off by one sign bit index, which is really
the size of the number which is being sign extended. Also, two calls in
arch/sparc/tlb.cc seemed to assume that the argument to that function
was modified in place, where really the new value is returned
separately. Move the call to sext so its return value is used and not
thrown away.
Change-Id: I86cb81ad243558e1a0d33def7f3eebe6973d6800
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
The remote GDB protocol encode thread IDs as positive integers, where 0
is a special value which indicates "pick any thread", and -1 is a
special value which indicates all threads.
The previous implementation would look like it worked handling the
special value -1 (for instance) because it see the '-' of "-1", stop
looking for digits, and return the default value 0.
This new implementation handles -1 as a special case, and will report an
error if no digits were found otherwise.
Also this change adds an encodeThreadId method to convert a ContextID
into a GDB thread ID by adding one to avoid the special value 0.
Change-Id: Iec54fbd9563d20a56011f48d50d69111ed1467b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44606
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
It was quite incovenient to declare tags. tags either
had to be added to the Source declaration of included
files, or using (with_tag()) would need to be added
with all the indirect sub-tags. For example,
Assume:
- B.cc refers to symbols in A.cc
- C.cc refers to symbols in B.cc (i.e., it needs A transitively)
- D.cc refers to symbols in A.cc and C.cc (i.e., it needs B trans.)
So either their SConscript would be:
Source('A.cc', add_tags=['B', 'D'])
Source('B.cc', add_tags='B')
Source('C.cc', add_tags='C')
Source('D.cc', add_tags='D')
GTest('A.test', 'A.test.cc', 'a.cc')
GTest('B.test', 'B.test.cc', with_tag('B'))
GTest('C.test', 'C.test.cc', with_any_tags('B', 'C'))
GTest('D.test', 'D.test.cc', with_any_tags('B', 'C', 'D'))
or:
Source('A.cc', add_tags=['B', 'C', 'D'])
Source('B.cc', add_tags=['B', 'C', 'D'])
Source('C.cc', add_tags=['C', 'D'])
Source('D.cc', add_tags='D')
GTest('A.test', 'A.test.cc', 'a.cc')
GTest('B.test', 'B.test.cc', with_tag('B'))
GTest('C.test', 'C.test.cc', with_tag('C'))
GTest('D.test', 'D.test.cc', with_tag('D'))
This change makes it simpler. The tag should be added
only to the files directly included by the functionality
being tagged. Using the same example:
Source('A.cc', add_tags=['B', 'D'])
Source('B.cc', add_tags='B')
Source('C.cc', add_tags='C')
Source('D.cc', add_tags='D')
env.TagImplies('B', 'A')
env.TagImplies('C', 'B')
env.TagImplies('D', ['A', 'C'])
GTest('A.test', 'A.test.cc', 'a.cc')
GTest('B.test', 'B.test.cc', with_tag('B'))
GTest('C.test', 'C.test.cc', with_tag('C'))
GTest('D.test', 'D.test.cc', with_tag('D'))
This also means that when a file no longer refers to
symbols from other file, or when it starts refering to
symbols from another file, one only needs to change
the dependencies of the tag directly being modified,
not the tags that rely on (imply) them. That is, on
the previous example, if C stops refering to symbols
from B, then tags that imply C do not need to be
modified:
env.TagImplies('B','A')
env.TagImplies('D', ['A', 'C'])
Change-Id: I5be07b01864f8d5df83f59002dfd2f01c73d5e09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43587
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Instead, create a new tool called EnvDefaults. This tool now needs
to be explicitly listed in the set of tools available through an
Environment, but that's easy to do in on place (all environments should
stem from main). Hijacking default like we were doing was (as far as I
can tell) not how that tool was intended to be used, and doing things
this way is a bit less hacky.
Also, we can split more Builders, etc, out of SConstruct, and these will
need to attach to main in the same way. We're going to need a list of
tools when main is constructed one way or the other, so we might as well
follow the rules.
Change-Id: I392e1639cb69d373c64970dccf45258000498cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40965
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.
Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Despite the generic sounding name and sort of generic contents, the
BaseDynInst was actually tied to the O3 CPU. Having the two independent
moving pieces created complexity but provided no real benefit. This was
evidenced by the fact that no CPU other than O3 actually used that
class.
Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
We have seen cases where the primary CPU was not able to bootstrap the
secondary CPUs in multicore tests (dual). The Linux booting process
"quietly" gives up (no panic) and it completes the booting without
bringing up the seondary CPU(s). This makes the dual test useless as it
is supposed to test SMP setups.
By adding a MatchFileRegex verifier, we make sure we are able to catch
these cases, correctly raising an error if not all CPUs are available.
We do this by inspecting the kernel log for the following print:
"CPU1: Booted secondary processor"
There are probably more resilient alternatives to a regex based check,
but those require a less minimal rootfs (the current
m5_exit.squashfs.arm64 FS has a single /sbin/init binary executing a
simple m5 exit operation)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I37e0882967443449d5fedfe3963bd25528a030f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44446
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
CfiMemory: This is modelling a flash memory adhering to the
Common Flash Interface (CFI):
JEDEC JESD68.01
JEDEC JEP137B
Intel Application Note 646
This is as of now a pure functional model of a flash controller: no
timing/power information has been encoded in it and it is therefore not
representive of a real device. Some voltage/timing values have
nevertheless been encoded in the CFI table. This is just a requirement
from the CFI specification: guest software might query those entries,
but they are not reflected in gem5 statistics.
The model is meant to be used to allow execution of flash drivers (e.g.
UEFI firmware storing EFI variables in non volatile memory)
JIRA: https://gem5.atlassian.net/browse/GEM5-913
Change-Id: Id99e331ac8237f3ecb69d618da0d7ca7b038cd1f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41495
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with recent versions of the Power ISA. This
allows the registers to be used for both 32-bit and 64-bit
execution modes.
It should be noted that in 32-bit mode, the use of upper
word is dependent on the instruction being executed and in
some cases, this may be undefined.
Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40881
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
New topology ripped from Fiji to support dGPU. A dGPU flag is added to
the config which is propogated to the driver. The emulated driver is
now able to properly deal with dGPU ioctls and mmaps. For now, dGPU
physical memory is allocated from the host, but this is easy to change
once we get a GPU memory controller up and running.
Change-Id: I594418482b12ec8fb2e4018d8d0371d56f4f51c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42214
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The Bridge SimObject, which hosts the CDC and SerDes functionality,
could be woken up out-of-order when changing frequencies in DVFS.
This change ensures there is no packet drop during the transition
times.
Change-Id: I40240dcb3e957217abd2d7ad22cc4f78809f7b49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44287
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Flitbuffers act as FIFOs for internal links and output queues
in routers. This change replaces the use of vectors with deque
for performance improvements. The older implementation of using
a vector combined with a heap sort was both incorrect and
inefficient.
Incorrect because flit buffers should act strictly
as FIFO, sorting them based on time changes the order which affects
functionality in the case of DVFS enabled NoCs.
Change-Id: Ieba40f85628b7c7255e86792d40b8ce3d7ac34b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44286
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The switch allocator implements a two step separable allocator and
utilizes port winner and vc winner data structures for functionality.
This improves the data structures used and their operations to improve
overall performance of the simulation. We start with an invalid output
port(-1) and an invalid vc(-1) and then allocate the outports
and vcs to inport.
Change-Id: I38b70ebdc1a54b8f748c2a5d510814bf139b9eaa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Previously we only rely on timestamp to schedule all phase change events
of tlm transactions in Gem5ToTlmBridge. However, it is valid to have
END_REQ and BEGIN_RESP of a transaction to be scheduled at the same
timestamp and the gem5 scheduler will not necessary order them in a
correct way.
This unfortunately breaks the code as sending a response before
accepting a request doesn't make sense at all and will trigger an
assertion failure.
In this CL we slightly increase the priority of END_REQ event so we can
always process phase change events in a correct order.
Change-Id: Ic33a92162c8c53af3887c7b04090115a38f96866
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44305
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.
This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss
Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
