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19d682c0ca
Typo fixed (PowerAnalysys --> PowerAnalysis)
2015-05-08 14:04:59 +02:00
cd8aeebe6f
Created an enumeration to the possible values of storage mode.
2015-05-08 12:52:49 +02:00
fd371795c7
Using relative paths instead of absolute paths in configuration files
2015-05-06 11:33:58 +02:00
16cbd15f47
Readme file updated with information about dramSys configuration
2015-05-06 10:51:07 +02:00
310e443776
Merge pull request #5 from fzeder/master
2015-04-27 15:20:19 +02:00
41993d87b5
Segfalut caused by misuse of sc_assert() fixed.
2015-04-27 14:36:09 +02:00
18025343cd
Warnings eliminated.
2015-04-24 11:20:44 +02:00
6cf6c6be95
Warnings eliminated.
2015-04-24 09:11:25 +02:00
ce7f85c3e1
Some fixes after review.
2015-04-21 16:54:07 +02:00
5898be7c67
Text enhanced
2015-04-21 16:08:22 +02:00
378544be26
Minor changes in text
2015-04-21 16:03:40 +02:00
1cb13725e2
Text enhanced.
2015-04-21 15:58:28 +02:00
ffb8f38a9a
Added more information about configuration files.
2015-04-21 15:51:07 +02:00
ed4b406954
Readme file improved but not yet finished.
2015-04-21 14:41:14 +02:00
c6dd5b1071
Merge pull request #4 from fzeder/master
2015-04-21 11:29:17 +02:00
381a26fed7
fixed hardcoded configuration in main.cpp
2015-04-21 11:19:46 +02:00
5cd24dc0fd
Merge branch 'ehses-master'
2015-04-09 10:33:54 +02:00
e1a7f1a0a5
removed namespace core
2015-04-09 10:33:25 +02:00
7f67a82287
added error model to the configs
2015-04-09 10:33:02 +02:00
0f8ad59a1e
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
2015-04-09 10:32:06 +02:00
268e839472
small changes in the metrics
2015-04-09 10:07:30 +02:00
2a587436d9
Fixed small bug
2015-04-09 10:01:27 +02:00
ce86b532c3
small changes and comments
2015-03-25 14:21:37 +01:00
836bacc76f
fixed overflow bug in StlPlayer
2015-03-23 13:40:24 +01:00
5fcd57a4e2
Fixed error in refresh manager and in backpressure release codepath
2015-03-23 08:43:18 +01:00
fe8ff6242d
bugfix of robert deadlock?
2015-02-23 17:12:17 +01:00
a5492a84d8
Merge branch 'master' of https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system
2015-02-17 22:48:10 +01:00
cffd844aaf
removed space
2015-02-17 22:46:31 +01:00
51f9a7f53f
test for in order check
2015-02-17 22:45:20 +01:00
aa615dae63
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2015-02-17 21:52:39 +01:00
c9a01d9a33
added better metric for utilisation
2015-02-17 21:50:15 +01:00
beddeccb64
Fixed bug in Fifostrict that caused deadlock
2015-02-17 09:22:58 +01:00
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer. Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
571e717224
removed some errors
2014-12-02 16:05:13 +01:00
e84a3cc99b
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
2014-12-02 15:25:48 +01:00
8ec02d3f2c
Merge pull request #1 from EIT-Wehn/master
2014-12-02 14:50:13 +01:00
905e75ca32
included errormodel which is presented in DATE paper
2014-12-02 14:44:46 +01:00
badcc37118
debug bums raus
2014-10-08 21:12:01 +02:00
f35cc43186
gute frage^^
2014-10-08 21:04:44 +02:00
a366ed8f91
easy error model from patrick implemented
2014-09-16 10:27:14 +02:00
e105d54045
added fix for bankgroups and ranks in addressdecoder
2014-09-10 16:10:07 +02:00
5a7efb4d88
merged
2014-09-08 15:03:10 +02:00
6ce8935097
fix on fifo hack
2014-09-08 14:59:28 +02:00
9fb90e9015
Experimantal change for a big FIFO
2014-09-08 13:09:52 +02:00
33a13d6bfd
status quo .. jetzt wirds tricky
2014-09-07 00:04:19 +02:00
938dbb3fdb
print mapping
2014-09-06 20:21:43 +02:00
30b1fbbd0c
added no powerdown option
2014-09-06 16:59:46 +02:00
e110d45e0e
Added Zoom by keys - and + Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-09-06 01:16:13 +02:00
2aa07bbbe6
Quick and Dirty XML - Refactoring necessary
2014-09-04 23:35:54 +02:00
8d864afb44
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-09-04 15:35:30 +02:00
1c7643b9b6
Changed analysis scripts
2014-09-04 15:35:01 +02:00
610dc6e6a5
changed fifo scheduler to strictly keep the order
2014-09-04 11:19:40 +02:00
320331164b
xml extended, sim config introduced
2014-09-03 18:52:32 +02:00
1807ef00f4
Added nbrOfColumns member variable
2014-09-03 15:11:46 +02:00
9cddd32a01
Changed #ifndef of trace generators' header file
2014-09-03 11:53:09 +02:00
7abf3c9958
Refactored TlmPacketGenerator in TraceGenerator
2014-09-03 11:39:41 +02:00
c5971ba2f5
merged conflicts
2014-09-03 10:37:39 +02:00
8722808a90
made traceplayer generic, so that different kind of traceplayers are supported
2014-09-03 10:27:04 +02:00
85a574fd5b
Configuration refactoring
2014-08-30 19:22:48 +02:00
fdc723a1bc
Merge branch 'master' of https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system
2014-08-29 13:10:01 +02:00
fcd029c6d8
Traceplayer now tolerates new lines in the Tracefiles
2014-08-29 12:23:13 +02:00
df6637b114
splitting config and memspec
2014-08-29 10:25:32 +02:00
540eb5445e
Merge pull request #2 from ehses/master
2014-08-28 09:58:23 +02:00
2ef6d35f97
Fixed for new drampower library
2014-08-28 09:52:38 +02:00
efc6094c13
memspec class
2014-08-27 09:43:42 +02:00
ea64dd8cea
Mapping will automatically generated
2014-08-07 15:16:40 +02:00
b008875fca
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-08-07 13:57:37 +02:00
fbf79645aa
Added some new metric scripts and Trace analysys tools
2014-08-07 13:36:27 +02:00
8e29063f76
added config for read/write grouper
2014-08-07 12:11:48 +02:00
b1142c4796
traceplayer can now parse data of write commands. Reorder buffer inserted
2014-08-07 12:06:04 +02:00
47580bcba3
added read/write grouper memconfig
2014-08-06 10:30:49 +02:00
767d03dfe9
modified rd/grouper
2014-08-06 10:02:56 +02:00
0bba004266
modified rd/write grouper
2014-08-06 09:37:42 +02:00
15f07b0017
precharge allchecker tRas, simulation memory
2014-08-05 19:33:16 +02:00
e38a872a11
added adressmapping to output filename
2014-08-05 19:02:48 +02:00
114bcf370f
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-08-05 17:01:46 +02:00
327608b691
commented out the saving part
2014-08-05 16:59:22 +02:00
609e568fbc
Added the tRAS timing constraint into the precharge checker
2014-08-05 16:58:15 +02:00
72bdce7a26
destructor
2014-08-05 00:22:03 +02:00
c88486d842
memcpy bug
2014-08-05 00:07:22 +02:00
fff7b9cd34
merged
2014-08-04 18:30:52 +02:00
bd245a9d90
reorder buffer
2014-08-04 18:27:33 +02:00
fe9f9ad233
changes on project file
2014-08-04 17:46:29 +02:00
6704dc2871
First approach for saving data, but there is an error with the memcopy in Dram.h
2014-08-04 17:31:25 +02:00
dc96ffd052
metrics: memory utilization
2014-08-04 13:02:52 +02:00
2f9cd66a73
Powerdowns bankwise have own command in protocoll now. one command for all banks on bank 0.
2014-07-30 23:37:56 +02:00
eb98c22188
merge
2014-07-30 22:10:28 +02:00
74456e530d
Update README.md
2014-07-30 03:04:57 +02:00
76ab26e2d7
refresh splitted in REFA REFB
2014-07-30 03:01:06 +02:00
62e7c8e65e
Changed to the lates DRAMPower
2014-07-29 16:21:59 +02:00
d402933502
New metric "memory utilization" defined
2014-07-29 16:21:07 +02:00
6ebafb9ece
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-07-29 15:18:30 +02:00
f74386a38e
Cleaned code
2014-07-29 15:18:12 +02:00
8af2f3b898
renamed colum to column in addressmapping. Error with large values on data bus should be resolved
2014-07-28 10:53:17 +02:00
79c7c84abb
Small buxfix update function included
2014-07-25 11:41:14 +02:00
8cdd36d064
small bug fixes regarding DRAMPower Library
2014-07-24 13:49:05 +02:00
df25e9ce6a
Changed Version to the new Main Branch of DRAMPower
2014-07-24 08:52:54 +02:00
3eb0d7eb8a
Fix for new DRAMPower library
2014-07-23 13:51:51 +02:00
f3f8dc4437
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-07-18 16:54:17 +02:00
acf06d995e
changed small things for DRAMPower
2014-07-18 13:20:45 +02:00
Éder Ferreira Zulian