derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

status quo .. jetzt wirds tricky

Browse Source
This commit is contained in:
Janik Schlemminger
2014-09-07 00:04:19 +02:00
parent 938dbb3fdb
commit 33a13d6bfd
8 changed files with 61 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
dram/resources/simulations/sim-batch.xml
View File

@@ -1,29 +1,25 @@
<simulation>
<simconfig>
<Debug value="1" />
</simconfig>
<memspecs>
<memspec src="/home/jonny/git/dram.vp.system/dram/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="/home/jonny/git/dram.vp.system/dram/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<!-- <memconfig>fr_fcfs.xml</memconfig>
-->
<memconfig src="/home/jonny/git/dram.vp.system/dram/resources/configs/memconfigs/fr_fcfs.xml">
<!-- <Debug value="1"></Debug>-->
</memconfig>
</memconfigs>
<tracesetups>
<simulation>
<simconfig>
<Debug value="1" />
</simconfig>
<memspecs>
<memspec src="/home/jonny/newconfigs/mems.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="/home/jonny/newconfigs/amc.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="/home/jonny/newconfigs/memc.xml">
</memconfig>
</memconfigs>
<tracesetups>
<tracesetup id="media">
<device clkMhz="800">chstone-sha_32.stl</device>
<tracesetup id="voco">
<!--<device clkMhz="200">test.stl</device>-->
<device clkMhz="200">eiersalat.stl</device>
</tracesetup>
</tracesetups>
</simulation>

4
dram/src/controller/Controller.h
View File

@@ -337,7 +337,9 @@ void Controller<BUSWIDTH>::frontendPEQCallback(tlm_generic_payload &payload, con
}
payload.set_response_status(tlm::TLM_OK_RESPONSE);
sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
scheduler->schedule(&payload);
//FIFOOOOOOOOOOO
//scheduler->schedule(&payload);
controllerCore->scheduleRequest(payload);
scheduleNextPayload();
}
else if (phase == END_RESP)

4
dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp
View File

@@ -12,9 +12,9 @@ namespace core {
void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
//return;
sc_assert(command.getCommand() == Command::Precharge);
ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank());
if (lastCommand.isValidCommand())
@@ -25,7 +25,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
}
else if (lastCommand.getCommand() == Command::Write)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
//command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
}
else if (lastCommand.getCommand() == Command::PDNAX)
{

16
dram/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -20,6 +20,22 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank());
//fifo patch
if(config.Scheduler == "FIFO")
{
//no access can accelerate other access
ScheduledCommand lastread = state.getLastCommand(Command::Read);
ScheduledCommand lastwrite = state.getLastCommand(Command::Write);
ScheduledCommand lastreada = state.getLastCommand(Command::ReadA);
ScheduledCommand lastwritea = state.getLastCommand(Command::WriteA);
command.delayToMeetConstraint(lastread.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastreada.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastwrite.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastwritea.getStart(), SC_ZERO_TIME);
}
if (lastCommand.isValidCommand())
{
if (lastCommand.getCommand() == Command::Activate)

16
dram/src/controller/core/scheduling/checker/WriteChecker.cpp
View File

@@ -18,6 +18,22 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank());
//fifo patch
if(config.Scheduler == "FIFO")
{
//no access can accelerate other access
ScheduledCommand lastread = state.getLastCommand(Command::Read);
ScheduledCommand lastwrite = state.getLastCommand(Command::Write);
ScheduledCommand lastreada = state.getLastCommand(Command::ReadA);
ScheduledCommand lastwritea = state.getLastCommand(Command::WriteA);
command.delayToMeetConstraint(lastread.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastreada.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastwrite.getStart(), SC_ZERO_TIME);
command.delayToMeetConstraint(lastwritea.getStart(), SC_ZERO_TIME);
}
if (lastCommand.isValidCommand())
{
if (lastCommand.getCommand() == Command::Activate)

4
dram/src/simulation/Simulation.cpp
View File

@@ -87,8 +87,8 @@ void Simulation::instantiateModules(const string &pathToResources, const std::ve
controller = new Controller<>("controller");
//reorder = new ReorderBuffer<>("reorder");
//player1 = new StlPlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].clkMhz, this);
player1 = new TraceGenerator<>("player1", 0, this);
player1 = new StlPlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].clkMhz, this);
//player1 = new TraceGenerator<>("player1", 0, this);
player2 = new StlPlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].clkMhz, this);
player3 = new StlPlayer<>("player3", pathToResources + string("traces/") + devices[2].trace, devices[2].clkMhz, this);
player4 = new StlPlayer<>("player4", pathToResources + string("traces/") + devices[3].trace, devices[3].clkMhz, this);

22
dram/src/simulation/SimulationManager.cpp
View File

@@ -29,6 +29,8 @@ void SimulationManager::loadSimulationsFromXML(string uri)
exportPath = getFileName(uri);
//basePath = boost::filesystem::path(uri).parent_path();
loadXML(uri, simulationdoc);
cout << "\t-> parsing simulation objects .." << endl;
@@ -39,9 +41,6 @@ void SimulationManager::loadSimulationsFromXML(string uri)
reportFatal("SimulationManager", "simulation node expected");
parseSimulationBatch(simulation);
//cout << "\t-> checking paths .." << endl;
//checkPaths();
cout << "\t-> simulation batches loaded successfully!\n" << endl;
for (auto batch : simulationBatches)
@@ -59,13 +58,8 @@ void SimulationManager::runSimulations()
for (auto& dramSetup : batch.dramSetups)
{
//string memconfig = getFileName(dramSetup.memconfig);
//string memspec = getFileName(dramSetup.memspec);
//string addressmappig = getFileName(dramSetup.addressmapping);
for (auto& traceSetup : batch.traceSetups)
{
// string exportname = exportPath + "/" + batch.simulationName + "/" + traceSetup.first + ".tdb";
string exportname = exportPath + "/" + traceSetup.first + ".tdb";
runSimulation(exportname, dramSetup, traceSetup.second);
}
@@ -77,11 +71,6 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
{
SimulationBatch batch;
//batch.simulationName = simulation->Attribute("id");
//string memspecUri;
//string addressmappingUri;
XMLElement* simconfig = simulation->FirstChildElement("simconfig");
XMLElement* memspecs = simulation->FirstChildElement("memspecs");
@@ -98,12 +87,10 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
for (XMLElement* memspec = memspecs->FirstChildElement("memspec"); memspec != NULL;
memspec = memspec->NextSiblingElement("memspec"))
{
//memspecUri = element->GetText();
for (XMLElement* addressmapping = addressmappings->FirstChildElement("addressmapping"); addressmapping != NULL;
addressmapping = addressmapping->NextSiblingElement("addressmapping"))
{
// addressmappingUri = element->GetText();
for (XMLElement* memconfig = memconfigs->FirstChildElement("memconfig");
memconfig != NULL; memconfig = memconfig->NextSiblingElement("memconfig"))
@@ -126,11 +113,6 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
}
void SimulationManager::checkPaths()
{
//reportFatal("Simulation Manager", "Not all paths in xml are valid");
}
void SimulationManager::runSimulation(string traceName, DramSetup dramSetup, vector<Device> traceSetup)
{
// int pid = fork();

1
dram/src/simulation/SimulationManager.h
View File

@@ -38,6 +38,7 @@ public:
private:
std::string resources;
std::string exportPath;
std::string basePath;
tinyxml2::XMLDocument simulationdoc;