diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 7541ef7a..8cf18562 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -1,29 +1,25 @@ - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - chstone-sha_32.stl + + + eiersalat.stl - + - diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index 3d5bfec8..88be6298 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -337,7 +337,9 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, con } payload.set_response_status(tlm::TLM_OK_RESPONSE); sendToFrontend(payload, END_REQ, SC_ZERO_TIME); - scheduler->schedule(&payload); + //FIFOOOOOOOOOOO + //scheduler->schedule(&payload); + controllerCore->scheduleRequest(payload); scheduleNextPayload(); } else if (phase == END_RESP) diff --git a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp index f76e08bd..58ed2ffb 100644 --- a/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -12,9 +12,9 @@ namespace core { void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) const { + //return; sc_assert(command.getCommand() == Command::Precharge); - ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) @@ -25,7 +25,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons } else if (lastCommand.getCommand() == Command::Write) { - command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR); + //command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR); } else if (lastCommand.getCommand() == Command::PDNAX) { diff --git a/dram/src/controller/core/scheduling/checker/ReadChecker.cpp b/dram/src/controller/core/scheduling/checker/ReadChecker.cpp index 3da3644b..7288701a 100644 --- a/dram/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -20,6 +20,22 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); + //fifo patch + if(config.Scheduler == "FIFO") + { + + //no access can accelerate other access + ScheduledCommand lastread = state.getLastCommand(Command::Read); + ScheduledCommand lastwrite = state.getLastCommand(Command::Write); + ScheduledCommand lastreada = state.getLastCommand(Command::ReadA); + ScheduledCommand lastwritea = state.getLastCommand(Command::WriteA); + + command.delayToMeetConstraint(lastread.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastreada.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastwrite.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastwritea.getStart(), SC_ZERO_TIME); + } + if (lastCommand.isValidCommand()) { if (lastCommand.getCommand() == Command::Activate) diff --git a/dram/src/controller/core/scheduling/checker/WriteChecker.cpp b/dram/src/controller/core/scheduling/checker/WriteChecker.cpp index bc2e29f6..dac9a578 100644 --- a/dram/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/dram/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -18,6 +18,22 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); + //fifo patch + if(config.Scheduler == "FIFO") + { + + //no access can accelerate other access + ScheduledCommand lastread = state.getLastCommand(Command::Read); + ScheduledCommand lastwrite = state.getLastCommand(Command::Write); + ScheduledCommand lastreada = state.getLastCommand(Command::ReadA); + ScheduledCommand lastwritea = state.getLastCommand(Command::WriteA); + + command.delayToMeetConstraint(lastread.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastreada.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastwrite.getStart(), SC_ZERO_TIME); + command.delayToMeetConstraint(lastwritea.getStart(), SC_ZERO_TIME); + } + if (lastCommand.isValidCommand()) { if (lastCommand.getCommand() == Command::Activate) diff --git a/dram/src/simulation/Simulation.cpp b/dram/src/simulation/Simulation.cpp index f3502465..dce93447 100644 --- a/dram/src/simulation/Simulation.cpp +++ b/dram/src/simulation/Simulation.cpp @@ -87,8 +87,8 @@ void Simulation::instantiateModules(const string &pathToResources, const std::ve controller = new Controller<>("controller"); //reorder = new ReorderBuffer<>("reorder"); - //player1 = new StlPlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].clkMhz, this); - player1 = new TraceGenerator<>("player1", 0, this); + player1 = new StlPlayer<>("player1", pathToResources + string("traces/") + devices[0].trace, devices[0].clkMhz, this); + //player1 = new TraceGenerator<>("player1", 0, this); player2 = new StlPlayer<>("player2", pathToResources + string("traces/") + devices[1].trace, devices[1].clkMhz, this); player3 = new StlPlayer<>("player3", pathToResources + string("traces/") + devices[2].trace, devices[2].clkMhz, this); player4 = new StlPlayer<>("player4", pathToResources + string("traces/") + devices[3].trace, devices[3].clkMhz, this); diff --git a/dram/src/simulation/SimulationManager.cpp b/dram/src/simulation/SimulationManager.cpp index 7cce0f65..7c161b5a 100644 --- a/dram/src/simulation/SimulationManager.cpp +++ b/dram/src/simulation/SimulationManager.cpp @@ -29,6 +29,8 @@ void SimulationManager::loadSimulationsFromXML(string uri) exportPath = getFileName(uri); + //basePath = boost::filesystem::path(uri).parent_path(); + loadXML(uri, simulationdoc); cout << "\t-> parsing simulation objects .." << endl; @@ -39,9 +41,6 @@ void SimulationManager::loadSimulationsFromXML(string uri) reportFatal("SimulationManager", "simulation node expected"); parseSimulationBatch(simulation); - //cout << "\t-> checking paths .." << endl; - //checkPaths(); - cout << "\t-> simulation batches loaded successfully!\n" << endl; for (auto batch : simulationBatches) @@ -59,13 +58,8 @@ void SimulationManager::runSimulations() for (auto& dramSetup : batch.dramSetups) { - //string memconfig = getFileName(dramSetup.memconfig); - //string memspec = getFileName(dramSetup.memspec); - //string addressmappig = getFileName(dramSetup.addressmapping); - for (auto& traceSetup : batch.traceSetups) { - // string exportname = exportPath + "/" + batch.simulationName + "/" + traceSetup.first + ".tdb"; string exportname = exportPath + "/" + traceSetup.first + ".tdb"; runSimulation(exportname, dramSetup, traceSetup.second); } @@ -77,11 +71,6 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation) { SimulationBatch batch; - //batch.simulationName = simulation->Attribute("id"); - - //string memspecUri; - //string addressmappingUri; - XMLElement* simconfig = simulation->FirstChildElement("simconfig"); XMLElement* memspecs = simulation->FirstChildElement("memspecs"); @@ -98,12 +87,10 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation) for (XMLElement* memspec = memspecs->FirstChildElement("memspec"); memspec != NULL; memspec = memspec->NextSiblingElement("memspec")) { - //memspecUri = element->GetText(); for (XMLElement* addressmapping = addressmappings->FirstChildElement("addressmapping"); addressmapping != NULL; addressmapping = addressmapping->NextSiblingElement("addressmapping")) { - // addressmappingUri = element->GetText(); for (XMLElement* memconfig = memconfigs->FirstChildElement("memconfig"); memconfig != NULL; memconfig = memconfig->NextSiblingElement("memconfig")) @@ -126,11 +113,6 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation) } -void SimulationManager::checkPaths() -{ - //reportFatal("Simulation Manager", "Not all paths in xml are valid"); -} - void SimulationManager::runSimulation(string traceName, DramSetup dramSetup, vector traceSetup) { // int pid = fork(); diff --git a/dram/src/simulation/SimulationManager.h b/dram/src/simulation/SimulationManager.h index 966e1731..432d8c1c 100644 --- a/dram/src/simulation/SimulationManager.h +++ b/dram/src/simulation/SimulationManager.h @@ -38,6 +38,7 @@ public: private: std::string resources; std::string exportPath; + std::string basePath; tinyxml2::XMLDocument simulationdoc;