derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

precharge allchecker tRas, simulation memory

Browse Source
This commit is contained in:
Janik Schlemminger
2014-08-05 19:33:16 +02:00
parent 114bcf370f
commit 15f07b0017
3 changed files with 21 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
dram/resources/simulations/sim-batch.xml
View File

@@ -16,7 +16,8 @@
<trace-setup id="media">
<device clkMhz="800">small.stl</device>
<!-- <device clkMhz="800">small.stl</device> -->
<device clkMhz="800">chstone-sha_32.stl</device>
</trace-setup>
</trace-setups>

6
dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -53,6 +53,12 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c
}
}
ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank());
if (lastActivate.isValidCommand())
{
command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS);
}
state.bus.moveCommandToNextFreeSlot(command);
}

67
dram/src/simulation/Dram.h
View File

@@ -30,7 +30,7 @@ using namespace core;
using namespace Data;
#define POWER
#define POWER //not better to define in simulation xml? also flag for storage simulation
#ifdef POWER
#define IFPOW(x) x
@@ -39,43 +39,6 @@ using namespace Data;
#endif
class column
{
private:
unsigned char * data;
unsigned int bytes;
public:
column()
{
bytes = 0;
data = NULL;
}
column(int bytes)
{
this->bytes = bytes;
data = new unsigned char[bytes];
}
~column()
{
delete data;
}
void set(unsigned char * payloadDataPtr)
{
memcpy(data, payloadDataPtr, bytes);
}
void get(unsigned char * payloadDataPtr)
{
memcpy(payloadDataPtr, data, bytes);
}
};
template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false,
unsigned int FIXED_BL_VALUE = 0>
struct Dram: sc_module
@@ -83,7 +46,7 @@ struct Dram: sc_module
tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
IFPOW(libDRAMPower *DRAMPower);
map< unsigned long int, column * > memory;
map< unsigned long int, unsigned char[BUSWIDTH/2] > memory;
SC_CTOR(Dram) : tSocket("socket")
{
@@ -128,28 +91,24 @@ struct Dram: sc_module
else if (phase == BEGIN_WR)
{
IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle));
//save data:
memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8);
sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload));
// Save:
//column * c = new column(16);
//c->set(payload.get_data_ptr());
//memory[payload.get_address()] = c;
}
else if (phase == BEGIN_RD)
{
IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle));
sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload));
// Load:
//if(memory.count(payload.get_address()) == 1)
//{
// column * c = memory[payload.get_address()];
// c->get(payload.get_data_ptr());
//}
//else
//{
// SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location");
//}
// Load data:
if(memory.count(payload.get_address()) == 1)
{
memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8);
}
else
{
SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location.");
}
}
else if (phase == BEGIN_WRA)
{