From 15f07b00176e084ae535af13e8b2ca88bf176445 Mon Sep 17 00:00:00 2001
From: Janik Schlemminger <schlemmi@rhrk.uni-kl.de>
Date: Tue, 5 Aug 2014 19:33:16 +0200
Subject: [PATCH] precharge allchecker tRas, simulation memory

---
 dram/resources/simulations/sim-batch.xml      |  3 +-
 .../checker/PrechargeAllChecker.cpp           |  6 ++
 dram/src/simulation/Dram.h                    | 67 ++++---------------
 3 files changed, 21 insertions(+), 55 deletions(-)

diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml
index 89adea06..b1f47a18 100644
--- a/dram/resources/simulations/sim-batch.xml
+++ b/dram/resources/simulations/sim-batch.xml
@@ -16,7 +16,8 @@
 
 
 <trace-setup id="media">
-      <device clkMhz="800">small.stl</device> 
+     <!-- <device clkMhz="800">small.stl</device> -->
+     <device clkMhz="800">chstone-sha_32.stl</device>
 </trace-setup>
     
   </trace-setups>
diff --git a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
index 112d4f90..92820e76 100644
--- a/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
+++ b/dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
@@ -53,6 +53,12 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c
         }
     }
 
+    ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank());
+    if (lastActivate.isValidCommand())
+    {
+        command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS);
+    }
+
     state.bus.moveCommandToNextFreeSlot(command);
 }
 
diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h
index 22e48d74..ba252c55 100644
--- a/dram/src/simulation/Dram.h
+++ b/dram/src/simulation/Dram.h
@@ -30,7 +30,7 @@ using namespace core;
 using namespace Data;
 
 
-#define POWER
+#define POWER //not better to define in simulation xml? also flag for storage simulation
 
 #ifdef POWER
         #define IFPOW(x) x
@@ -39,43 +39,6 @@ using namespace Data;
 #endif
 
 
-class column
-{
-    private:
-
-    unsigned char * data;
-    unsigned int bytes;
-
-    public:
-
-    column()
-    {
-        bytes = 0;
-        data = NULL;
-    }
-
-    column(int bytes)
-    {
-        this->bytes = bytes;
-        data = new unsigned char[bytes];
-    }
-
-    ~column()
-    {
-        delete data;
-    }
-
-    void set(unsigned char * payloadDataPtr)
-    {
-        memcpy(data, payloadDataPtr, bytes);
-    }
-
-    void get(unsigned char * payloadDataPtr)
-    {
-        memcpy(payloadDataPtr, data, bytes);
-    }
-};
-
 template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false,
         unsigned int FIXED_BL_VALUE = 0>
 struct Dram: sc_module
@@ -83,7 +46,7 @@ struct Dram: sc_module
     tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
     IFPOW(libDRAMPower *DRAMPower);
 
-    map< unsigned long int, column * > memory;
+    map< unsigned long int, unsigned char[BUSWIDTH/2] > memory;
 
     SC_CTOR(Dram) : tSocket("socket")
     {
@@ -128,28 +91,24 @@ struct Dram: sc_module
         else if (phase == BEGIN_WR)
         {
             IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle));
+            //save data:
+            memcpy(&memory[payload.get_address()], payload.get_data_ptr(), BUSWIDTH/8);
             sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
-
-            // Save:
-            //column * c = new column(16);
-            //c->set(payload.get_data_ptr());
-            //memory[payload.get_address()] = c;
         }
         else if (phase == BEGIN_RD)
         {
             IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle));
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
 
-            // Load:
-            //if(memory.count(payload.get_address()) == 1)
-            //{
-            //    column * c = memory[payload.get_address()];
-            //    c->get(payload.get_data_ptr());
-            //}
-            //else
-            //{
-            //    SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location");
-            //}
+            // Load data:
+            if(memory.count(payload.get_address()) == 1)
+            {
+                memcpy(payload.get_data_ptr(), &memory[payload.get_address()], BUSWIDTH/8);
+            }
+            else
+            {
+                SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location.");
+            }
         }
         else if (phase == BEGIN_WRA)
         {