derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system

Browse Source
This commit is contained in:
Matthias Jung
2015-02-17 21:52:39 +01:00
parent c9a01d9a33 beddeccb64
commit aa615dae63
4 changed files with 39 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
dram/resources/configs/memconfigs/fifo.xml
View File

@@ -2,7 +2,7 @@
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="50" />
<Scheduler value="FIFO" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="TimeoutPDN" />
<PowerDownTimeout value="100" />

9
dram/resources/configs/memconfigs/fifoStrict.xml Normal file
View File

@@ -0,0 +1,9 @@
<memconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="50" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="TimeoutPDN" />
<PowerDownTimeout value="100" />
</memconfig>

28
dram/resources/simulations/sim-batch.xml
View File

@@ -1,4 +1,4 @@
<simulation>
<!-- <simulation>
<simconfig>
<Debug value="1" />
<DatabaseRecording value="1" />
@@ -17,9 +17,33 @@
<tracesetups>
<tracesetup id="fifo">
<!--<device clkMhz="200">test.stl</device>-->
<device clkMhz="200">test.stl</device>-
<device clkMhz="200">mediabench-epic_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>
-->
<simulation>
<simconfig>
<Debug value="1" />
<DatabaseRecording value="1" />
<PowerAnalysys value="1" />
</simconfig>
<memspecs>
<memspec src="/home/jungma/projects/dram.vp.system/dram/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="/home/jungma/projects/dram.vp.system/dram/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="/home/jungma/projects/dram.vp.system/dram/resources/configs/memconfigs/fifo.xml"/>
</memconfigs>
<tracesetups>
<tracesetup id="fifo">
<device clkMhz="200">voco2.stl</device>
</tracesetup>
</tracesetups>
</simulation>

17
dram/src/controller/scheduler/FifoStrict.cpp
View File

@@ -28,20 +28,9 @@ void FifoStrict::NotifyBeginRD()
if(buffer.size() > 0)
{
// If the new front element was orginally blocked, because it had to wait on the preceeding fron element, we have to unblock it.
// We only have to unblock if the new fron element is waiting for a RD/WR operation
if(commandIsIn(getNextCommand(*buffer.front()), {Command::Read, Command::Write, Command::ReadA, Command::WriteA})
&& !controllerCore.bankIsBusy(DramExtension::getBank(buffer.front())))
{
printDebugMessage("Unblocking front element.\n");
controller.scheduleNextFromScheduler(DramExtension::getBank(buffer.front()));
}
// If the new front element is on the same bank as the old one, we have let it make progress, even when the next command is not a RD/WR
// because we are not calling scheduleNextFromScheduler from the calling side
else if(oldFrontElementBank == DramExtension::getBank(*buffer.front()))
{
controller.scheduleNextFromScheduler(DramExtension::getBank(buffer.front()));
}
// If the new front element was orginally blocked, because it had to wait on the old front element, we have to call
// controller.scheduleNextFromScheduler explicitly, otherwise there will be a deadlock in the system
controller.scheduleNextFromScheduler(DramExtension::getBank(buffer.front()));
}
}