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memspec class

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This commit is contained in:
Janik Schlemminger
2014-08-27 09:43:42 +02:00
parent 8e29063f76
commit efc6094c13
29 changed files with 204 additions and 207 deletions
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6
dram/dramSys/dramSys.pro
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@@ -15,7 +15,7 @@ LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
INCLUDEPATH += /opt/systemc/include
INCLUDEPATH += /opt/boost/include
INCLUDEPATH += /opt/sqlite3/include
INCLUDEPATH += /opt/xerces-c-3.1.1/include
INCLUDEPATH += /opt/xerces/include
INCLUDEPATH += ../src/common/third_party/DRAMPower/src
INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
@@ -79,7 +79,6 @@ HEADERS += \
../src/common/protocol.h \
../src/common/dramExtension.h \
../src/common/DebugManager.h \
../src/controller/core/configuration/TimingConfiguration.h \
../src/controller/core/configuration/MemSpecLoader.h \
../src/controller/core/configuration/Configuration.h \
../src/controller/core/powerdown/PowerDownManagerTimeout.h \
@@ -123,5 +122,6 @@ HEADERS += \
../src/common/libDRAMPower.h \
../src/controller/core/RowBufferStates.h \
../src/controller/scheduler/readwritegrouper.h \
../src/simulation/ReorderBuffer.h
../src/simulation/ReorderBuffer.h \
../src/controller/core/configuration/MemSpec.h

2
dram/resources/simulations/sim-batch.xml
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@@ -5,7 +5,7 @@
<memconfigs>
<!-- <memconfig>fr_fcfs.xml</memconfig>
--> <memconfig>grouper.xml</memconfig>
--> <memconfig>fr_fcfs.xml</memconfig>
</memconfigs>
<trace-setups>

4
dram/src/common/TlmRecorder.cpp
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@@ -240,8 +240,8 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 1, totalNumTransactions - 1);
sqlite3_bind_int64(insertGeneralInfoStatement, 2, simulationTimeCoveredByRecording.value());
sqlite3_bind_int(insertGeneralInfoStatement, 3,
core::Configuration::getInstance().NumberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 4, core::Configuration::getInstance().Timings.clk.value());
core::Configuration::getInstance().memSpec.NumberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 4, core::Configuration::getInstance().memSpec.clk.value());
sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 6, memconfig.c_str(), memconfig.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 7, memspec.c_str(), memspec.length(), NULL);

2
dram/src/common/dramExtension.cpp
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@@ -184,7 +184,7 @@ bool operator !=(const Row& lhs, const Row& rhs)
const Row Row::operator ++()
{
id = (id + 1) % core::Configuration::getInstance().NumberOfRows;
id = (id + 1) % core::Configuration::getInstance().memSpec.NumberOfRows;
return *this;
}

6
dram/src/controller/Controller.h
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@@ -23,7 +23,7 @@
#include "../common/TlmRecorder.h"
#include "../common/Utils.h"
#include "core/configuration/Configuration.h"
#include "core/configuration/TimingConfiguration.h"
#include "core/configuration/MemSpec.h"
#include "core/Command.h"
#include "core/ControllerCore.h"
#include "core/ControllerState.h"
@@ -310,12 +310,12 @@ tlm_sync_enum Controller<BUSWIDTH>::nb_transport_fw(tlm_generic_payload &payload
{
TlmRecorder::getInstance().recordPhase(payload, phase, fwDelay + sc_time_stamp());
frontendPEQ.notify(payload, phase,
clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay) + Configuration::getInstance().Timings.clk);
clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay) + Configuration::getInstance().memSpec.clk);
}
else if (phase == END_RESP)
{
TlmRecorder::getInstance().recordPhase(payload, phase,
fwDelay + sc_time_stamp() + Configuration::getInstance().Timings.clk);
fwDelay + sc_time_stamp() + Configuration::getInstance().memSpec.clk);
frontendPEQ.notify(payload, phase, clkAlign(sc_time_stamp() + fwDelay) - (sc_time_stamp() + fwDelay));
}
return TLM_ACCEPTED;

2
dram/src/controller/core/ControllerCore.cpp
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@@ -166,7 +166,7 @@ const std::vector<Bank>& ControllerCore::getBanks()
if (banks.size() == 0)
{
for (unsigned int i = 0; i < config.NumberOfBanks; i++)
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; i++)
{
banks.push_back(Bank(i));
}

10
dram/src/controller/core/ControllerState.cpp
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@@ -20,7 +20,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command)
{
ScheduledCommand max;
for (unsigned int i = 0; i < config->NumberOfBanks; ++i)
for (unsigned int i = 0; i < config->memSpec.NumberOfBanks; ++i)
{
ScheduledCommand current = getLastCommand(command, Bank(i));
if (current.getStart() > max.getStart())
@@ -36,7 +36,7 @@ const ScheduledCommand ControllerState::getLastScheduledCommand()
for(Command cmd : getAllCommands())
{
for(Bank bank : Configuration::getInstance().getBanks())
for(Bank bank : Configuration::getInstance().memSpec.getBanks())
{
ScheduledCommand& current = lastScheduledByCommandAndBank[cmd][bank];
if (current.getStart() > lastCommand.getStart())
@@ -109,12 +109,12 @@ void ControllerState::cleanUp(sc_time time)
vector<ScheduledCommand> tmp;
for(ScheduledCommand& command: lastDataStrobeCommands)
{
if(command.getEnd() >= time || getDistance(command.getEnd(), time) <= config->Timings.tDataStrobeHistory())
if(command.getEnd() >= time || getDistance(command.getEnd(), time) <= config->memSpec.tDataStrobeHistory())
tmp.push_back(command);
}
lastDataStrobeCommands = tmp;
if(time >= config->Timings.tActHistory())
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory()));
if(time >= config->memSpec.tActHistory())
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->memSpec.tActHistory()));
}
} /* namespace controller */

2
dram/src/controller/core/ControllerState.h
View File

@@ -23,7 +23,7 @@ class ControllerState
{
public:
ControllerState(Configuration* config) :
rowBufferStates(), bus(config->Timings.clk), config(config)
rowBufferStates(), bus(config->memSpec.clk), config(config)
{
}
virtual ~ControllerState()

4
dram/src/controller/core/RowBufferStates.cpp
View File

@@ -48,7 +48,7 @@ void RowBufferState::closeRowBuffer(Bank bank)
bool RowBufferState::allRowBuffersAreClosed() const
{
for(unsigned int i=0; i<Configuration::getInstance().NumberOfBanks;++i)
for(unsigned int i=0; i<Configuration::getInstance().memSpec.NumberOfBanks;++i)
{
if(rowBufferIsOpen(Bank(i)))
return false;
@@ -58,7 +58,7 @@ bool RowBufferState::allRowBuffersAreClosed() const
void RowBufferState::closeAllRowBuffers()
{
for(unsigned int i=0; i<Configuration::getInstance().NumberOfBanks;++i)
for(unsigned int i=0; i<Configuration::getInstance().memSpec.NumberOfBanks;++i)
{
rowsInRowBuffers[Bank(i)] = Row::NO_ROW;
}

16
dram/src/controller/core/TimingCalculation.cpp
View File

@@ -6,7 +6,7 @@
*/
#include "TimingCalculation.h"
#include "configuration/TimingConfiguration.h"
#include "configuration/MemSpec.h"
#include "ControllerCore.h"
#include "../../common/DebugManager.h"
#include "configuration/Configuration.h"
@@ -30,7 +30,7 @@ const sc_time FrequencyToClk(double frequencyMhz)
const sc_time clkAlign(sc_time time, Alignment alignment)
{
sc_time clk = Configuration::getInstance().Timings.clk;
sc_time clk = Configuration::getInstance().memSpec.clk;
if (alignment == UP)
return ceil(time / clk) * clk;
else
@@ -39,7 +39,7 @@ const sc_time clkAlign(sc_time time, Alignment alignment)
sc_time getExecutionTime(Command command, tlm::tlm_generic_payload& payload)
{
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
if (command == Command::Precharge || command == Command::PrechargeAll)
{
@@ -87,7 +87,7 @@ sc_time getExecutionTime(Command command, tlm::tlm_generic_payload& payload)
sc_time getMinExecutionTimeForPowerDownCmd(Command command)
{
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
if (command == Command::PDNA || command == Command::PDNP)
{
return config.tCKE;
@@ -112,20 +112,20 @@ bool isClkAligned(sc_time time, sc_time clk)
sc_time getReadAccessTime()
{
Configuration& config = Configuration::getInstance();
return (config.BurstLength / config.DataRate)*config.Timings.clk;
return (config.memSpec.BurstLength / config.memSpec.DataRate)*config.memSpec.clk;
}
sc_time getWriteAccessTime()
{
Configuration& config = Configuration::getInstance();
if (config.DataRate == 1)
if (config.memSpec.DataRate == 1)
{
return config.Timings.clk * (config.BurstLength-1) ;
return config.memSpec.clk * (config.memSpec.BurstLength-1) ;
}
else
{
return config.Timings.clk * (config.BurstLength / config.DataRate);
return config.memSpec.clk * (config.memSpec.BurstLength / config.memSpec.DataRate);
}
}

14
dram/src/controller/core/configuration/Configuration.cpp
View File

@@ -21,20 +21,6 @@ Configuration::Configuration()
loader.loadConfiguration(*this, Configuration::memspecUri, Configuration::memconfigUri);
}
const std::vector<Bank>& Configuration::getBanks() const
{
static std::vector<Bank> banks;
if (banks.size() == 0)
{
for (unsigned int i = 0; i < NumberOfBanks; i++)
{
banks.push_back(Bank(i));
}
}
return banks;
}
} /* namespace core */

38
dram/src/controller/core/configuration/Configuration.h
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@@ -10,7 +10,7 @@
#include <systemc.h>
#include <string>
#include "TimingConfiguration.h"
#include "MemSpec.h"
namespace core{
@@ -30,35 +30,21 @@ struct Configuration
}
//MemConfiguration
bool BankwiseLogic;
bool OpenPagePolicy;
bool AdaptiveOpenPagePolicy;
bool RefreshAwareScheduling;
unsigned int MaxNrOfTransactions;
bool BankwiseLogic = false;
bool OpenPagePolicy = true;
bool AdaptiveOpenPagePolicy = false;
bool RefreshAwareScheduling = false;
unsigned int MaxNrOfTransactions = 50;
std::string Scheduler;
unsigned int Capsize;
bool databaseRecordingEnabled;
//MemSpecification
std::string MemoryId;
std::string MemoryType;
unsigned int NumberOfBanks;
unsigned int NumberOfBankGroups;
unsigned int BurstLength;
unsigned int nActivate;
unsigned int DataRate;
unsigned int NumberOfRows;
bool recordingIsEnabled;
// Powerdown Mode
sc_time powerDownTimeout;
unsigned int Capsize = 5;
sc_time powerDownTimeout = 3*memSpec.clk;
PowerDownMode powerDownMode;
//MemTimings
TimingConfiguration Timings;
//Memory Specification (from DRAM Power XML)
MemSpec memSpec;
const std::vector<Bank>& getBanks() const;
//Simulation Configuration
bool databaseRecordingEnabled = true;
private:
Configuration();

37
dram/src/controller/core/configuration/TimingConfiguration.h → dram/src/controller/core/configuration/MemSpec.h
View File

@@ -1,12 +1,12 @@
/*
* TimingConfiguration.h
* MemSpec.h
*
* Created on: Mar 6, 2014
* Author: jonny
*/
#ifndef TIMINGS_H_
#define TIMINGS_H_
#ifndef MemSpec_H_
#define MemSpec_H_
#include <systemc.h>
#include <map>
@@ -21,12 +21,37 @@ struct RefreshTiming
sc_time tREFI;
};
struct TimingConfiguration
struct MemSpec
{
TimingConfiguration()
MemSpec()
{
//default DDR4
}
const std::vector<Bank>& getBanks() const
{
static std::vector<Bank> banks;
if (banks.size() == 0)
{
for (unsigned int i = 0; i < NumberOfBanks; i++)
{
banks.push_back(Bank(i));
}
}
return banks;
}
std::string MemoryId = "not defined.";
std::string MemoryType = "not defined.";
unsigned int NumberOfBanks;
unsigned int NumberOfBankGroups;
unsigned int BurstLength;
unsigned int nActivate;
unsigned int DataRate;
unsigned int NumberOfRows;
sc_time clk;
sc_time tRP; //precharge-time (pre -> act same bank)
sc_time tRAS; //active-time (act -> pre same bank)
@@ -64,4 +89,4 @@ struct TimingConfiguration
} /* namespace core */
#endif /* TimingConfiguration_H_ */
#endif /* MemSpec_H_ */

150
dram/src/controller/core/configuration/MemSpecLoader.cpp
View File

@@ -6,7 +6,7 @@
*/
#include "MemSpecLoader.h"
#include "TimingConfiguration.h"
#include "MemSpec.h"
#include "../TimingCalculation.h"
using namespace tinyxml2;
@@ -53,21 +53,21 @@ void MemSpecLoader::loadMemConfig(Configuration& config, XMLElement* memconfig)
{
config.powerDownMode = PowerDownMode::TimeoutSREF;
}
config.powerDownTimeout = queryUIntParameter(configuration, "powerDownTimeout") * config.Timings.clk;
config.powerDownTimeout = queryUIntParameter(configuration, "powerDownTimeout") * config.memSpec.clk;
config.databaseRecordingEnabled = queryBoolParameter(configuration, "databaseRecordingEnabled");
}
void MemSpecLoader::loadMemSpec(Configuration& config, XMLElement* memspec)
{
config.MemoryId = queryStringParameter(memspec, "memoryId");
config.MemoryType = queryStringParameter(memspec, "memoryType");
config.memSpec.MemoryId = queryStringParameter(memspec, "memoryId");
config.memSpec.MemoryType = queryStringParameter(memspec, "memoryType");
if (config.MemoryType == "DDR4")
if (config.memSpec.MemoryType == "DDR4")
{
loadDDR4(config, memspec);
}
else if (config.MemoryType == "WIDEIO_SDR")
else if (config.memSpec.MemoryType == "WIDEIO_SDR")
{
loadWideIO(config, memspec);
}
@@ -82,47 +82,47 @@ void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
//MemSpecification
XMLElement* architecture = memspec->FirstChildElement("memarchitecturespec");
config.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups");
config.BurstLength = queryUIntParameter(architecture, "burstLength");
config.nActivate = 4;
config.DataRate = queryUIntParameter(architecture, "dataRate");
config.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups");
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 4;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
//MemTimings
XMLElement* timings = memspec->FirstChildElement("memtimingspec");
double clkMhz = queryDoubleParameter(timings, "clkMhz");
config.Timings.clk = FrequencyToClk(clkMhz);
sc_time clk = config.Timings.clk;
config.Timings.tRP = clk * queryUIntParameter(timings, "RP");
config.Timings.tRAS = clk * queryUIntParameter(timings, "RAS");
config.Timings.tRC = clk * queryUIntParameter(timings, "RC");
config.Timings.tRTP = clk * queryUIntParameter(timings, "RTP");
config.Timings.tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
config.Timings.tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
config.Timings.tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
config.Timings.tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
config.Timings.tRCD = clk * queryUIntParameter(timings, "RCD");
config.Timings.tNAW = clk * queryUIntParameter(timings, "FAW");
config.Timings.tRL = clk * queryUIntParameter(timings, "RL");
config.Timings.tWL = clk * queryUIntParameter(timings, "WL");
config.Timings.tWR = clk * queryUIntParameter(timings, "WR");
config.Timings.tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
config.Timings.tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
config.Timings.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.Timings.tCKE = clk * queryUIntParameter(timings, "CKE");
config.Timings.tXP = clk * queryUIntParameter(timings, "XP");
config.Timings.tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.Timings.tXSR = clk * queryUIntParameter(timings, "XS");
config.Timings.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.Timings.tAL = clk * queryUIntParameter(timings, "AL");
config.Timings.tRFC = clk * queryUIntParameter(timings, "RFC");
config.Timings.tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec.clk = FrequencyToClk(clkMhz);
sc_time clk = config.memSpec.clk;
config.memSpec.tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL");
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI");
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i)
{
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, config.Timings.tREFI);
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, config.memSpec.tREFI);
}
}
@@ -131,48 +131,48 @@ void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec)
//MemSpecification
XMLElement* architecture = memspec->FirstChildElement("memarchitecturespec");
config.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.NumberOfBankGroups = 1;
config.BurstLength = queryUIntParameter(architecture, "burstLength");
config.nActivate = 2;
config.DataRate = queryUIntParameter(architecture, "dataRate");
config.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.memSpec.NumberOfBankGroups = 1;
config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength");
config.memSpec.nActivate = 2;
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
//MemTimings
XMLElement* timings = memspec->FirstChildElement("memtimingspec");
double clkMhz = queryDoubleParameter(timings, "clkMhz");
sc_time clk = sc_time(1 / clkMhz, SC_US);
config.Timings.clk = clk;
config.memSpec.clk = clk;
config.Timings.tRP = clk * queryUIntParameter(timings, "RP");
config.Timings.tRAS = clk * queryUIntParameter(timings, "RAS");
config.Timings.tRC = clk * queryUIntParameter(timings, "RC");
config.Timings.tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.Timings.tRRD_L = config.Timings.tRRD_S;
config.Timings.tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.Timings.tCCD_L = config.Timings.tCCD_S;
config.Timings.tRCD = clk * queryUIntParameter(timings, "RCD");
config.Timings.tNAW = clk * queryUIntParameter(timings, "TAW");
config.Timings.tRL = clk * queryUIntParameter(timings, "RL");
config.Timings.tWL = clk * queryUIntParameter(timings, "WL");
config.Timings.tWR = clk * queryUIntParameter(timings, "WR");
config.Timings.tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.Timings.tWTR_L = config.Timings.tWTR_S;
config.Timings.tRTP = clk * queryUIntParameter(timings, "RTP");
config.Timings.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.Timings.tCKE = clk * queryUIntParameter(timings, "CKE");
config.Timings.tXP = clk * queryUIntParameter(timings, "XP");
config.Timings.tXPDLL = config.Timings.tXP;
config.Timings.tXSR = clk * queryUIntParameter(timings, "XS");
config.Timings.tXSRDLL = config.Timings.tXSR;
config.Timings.tAL = clk * queryUIntParameter(timings, "AL");
config.Timings.tRFC = clk * queryUIntParameter(timings, "RFC");
config.Timings.tREFI = clk * queryUIntParameter(timings, "REFI");
config.memSpec.tRP = clk * queryUIntParameter(timings, "RP");
config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS");
config.memSpec.tRC = clk * queryUIntParameter(timings, "RC");
config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD");
config.memSpec.tRRD_L = config.memSpec.tRRD_S;
config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD");
config.memSpec.tCCD_L = config.memSpec.tCCD_S;
config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD");
config.memSpec.tNAW = clk * queryUIntParameter(timings, "TAW");
config.memSpec.tRL = clk * queryUIntParameter(timings, "RL");
config.memSpec.tWL = clk * queryUIntParameter(timings, "WL");
config.memSpec.tWR = clk * queryUIntParameter(timings, "WR");
config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR");
config.memSpec.tWTR_L = config.memSpec.tWTR_S;
config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP");
config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE");
config.memSpec.tXP = clk * queryUIntParameter(timings, "XP");
config.memSpec.tXPDLL = config.memSpec.tXP;
config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS");
config.memSpec.tXSRDLL = config.memSpec.tXSR;
config.memSpec.tAL = clk * queryUIntParameter(timings, "AL");
config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC");
config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI");
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
config.memSpec.refreshTimings.clear();
for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i)
{
config.Timings.refreshTimings[Bank(i)] = RefreshTiming(config.Timings.tRFC, config.Timings.tREFI);
config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, config.memSpec.tREFI);
}
}

2
dram/src/controller/core/refresh/RefreshManager.cpp
View File

@@ -15,7 +15,7 @@ using namespace tlm;
namespace core {
RefreshManager::RefreshManager(ControllerCore& controller) :
controller(controller), timing(controller.config.Timings.refreshTimings[Bank(0)]), nextPlannedRefresh(SC_ZERO_TIME)
controller(controller), timing(controller.config.memSpec.refreshTimings[Bank(0)]), nextPlannedRefresh(SC_ZERO_TIME)
{
setupTransactions();
planNextRefresh();

2
dram/src/controller/core/refresh/RefreshManager.h
View File

@@ -9,7 +9,7 @@
#define REFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "../configuration/TimingConfiguration.h"
#include "../configuration/MemSpec.h"
namespace core {

2
dram/src/controller/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -67,7 +67,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload,
void RefreshManagerBankwise::planNextRefresh(Bank bank)
{
nextPlannedRefreshs[bank] += Configuration::getInstance().Timings.refreshTimings[bank].tREFI;
nextPlannedRefreshs[bank] += Configuration::getInstance().memSpec.refreshTimings[bank].tREFI;
controller.wrapper.send(REFTrigger, nextPlannedRefreshs[bank], refreshPayloads[bank]);
}

2
dram/src/controller/core/refresh/RefreshManagerBankwise.h
View File

@@ -10,7 +10,7 @@
#include "../scheduling/CommandSchedule.h"
#include "../../../common/dramExtension.h"
#include "../configuration/TimingConfiguration.h"
#include "../configuration/MemSpec.h"
#include "IRefreshManager.h"
namespace core {

2
dram/src/controller/core/scheduling/ScheduledCommand.cpp
View File

@@ -95,7 +95,7 @@ TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const
|| getCommand() == Command::Write
|| getCommand() == Command::WriteA);
TimingConfiguration& timings = Configuration::getInstance().Timings;
MemSpec& timings = Configuration::getInstance().memSpec;
if (getCommand() == Command::Read || getCommand() == Command::ReadA)
{

24
dram/src/controller/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -25,28 +25,28 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommandOnBank.getCommand() == Command::Precharge)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::ReadA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRTP + config.Timings.tRP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRTP + config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::WriteA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(),
config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR + config.Timings.tRP);
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::AutoRefresh)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRFC);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRFC);
}
else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXP);
}
else if (lastCommandOnBank.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXSR);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXSR);
}
else
reportFatal("Activate Checker", "Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));
@@ -57,7 +57,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
while (!(state.bus.isFree(command.getStart()) && satsfies_activateToActivate_differentBank(command)
&& satisfies_nActivateWindow(command)))
{
command.delayStart(config.Timings.clk);
command.delayStart(config.memSpec.clk);
}
}
@@ -67,7 +67,7 @@ void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank(ScheduledComm
ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::Activate, command.getBank());
if (lastActivateOnBank.isValidCommand())
{
command.delayToMeetConstraint(lastActivateOnBank.getStart(), config.Timings.tRC);
command.delayToMeetConstraint(lastActivateOnBank.getStart(), config.memSpec.tRC);
}
}
@@ -76,7 +76,7 @@ bool ActivateChecker::satsfies_activateToActivate_differentBank(ScheduledCommand
for (auto act : state.lastActivates)
{
sc_time time = act.first;
sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? config.Timings.tRRD_L : config.Timings.tRRD_S;
sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? config.memSpec.tRRD_L : config.memSpec.tRRD_S;
if ((time < command.getStart() && command.getStart() - time < tRRD)
|| (command.getStart() <= time && time - command.getStart() < tRRD))
@@ -92,17 +92,17 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand& command) const
* command in a copied set (not necessarily the last in time),
* and check if the n-act constraint holds for the whole set.
*/
if (state.lastActivates.size() >= config.nActivate)
if (state.lastActivates.size() >= config.memSpec.nActivate)
{
map<sc_time, ScheduledCommand> lastActivates = state.lastActivates;
lastActivates.emplace(command.getStart(), command);
auto upper = lastActivates.begin();
advance(upper, config.nActivate);
advance(upper, config.memSpec.nActivate);
auto lower = lastActivates.begin();
while (upper != lastActivates.end())
{
if (upper->first - lower->first < config.Timings.tNAW)
if (upper->first - lower->first < config.memSpec.tNAW)
return false;
++upper;
++lower;

18
dram/src/controller/core/scheduling/checker/PowerDownChecker.cpp
View File

@@ -24,30 +24,30 @@ void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
if (lastCommandOnBank.getCommand() == Command::Read || lastCommandOnBank.getCommand() == Command::ReadA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(),
config.Timings.tRL + getReadAccessTime() + config.Timings.clk);
config.memSpec.tRL + getReadAccessTime() + config.memSpec.clk);
}
else if (lastCommandOnBank.getCommand() == Command::Write)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(),
config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR);
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
}
else if (lastCommandOnBank.getCommand() == Command::WriteA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(),
config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR + config.Timings.clk);
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + config.memSpec.clk);
}
else if (lastCommandOnBank.getCommand() == Command::AutoRefresh)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRFC);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRFC);
}
else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXP);
}
else if (lastCommandOnBank.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXSR);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXSR);
}
else
@@ -59,15 +59,15 @@ void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
else if (command.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(state.getLastCommand(Command::PDNA).getStart(), config.Timings.tCKE);
command.delayToMeetConstraint(state.getLastCommand(Command::PDNA).getStart(), config.memSpec.tCKE);
}
else if (command.getCommand() == Command::PDNPX)
{
command.delayToMeetConstraint(state.getLastCommand(Command::PDNP).getStart(), config.Timings.tCKE);
command.delayToMeetConstraint(state.getLastCommand(Command::PDNP).getStart(), config.memSpec.tCKE);
}
else if (command.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(state.getLastCommand(Command::SREF).getStart(), config.Timings.tCKESR);
command.delayToMeetConstraint(state.getLastCommand(Command::SREF).getStart(), config.memSpec.tCKESR);
}
state.bus.moveCommandToNextFreeSlot(command);

18
dram/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -14,38 +14,38 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c
{
sc_assert(command.getCommand() == Command::PrechargeAll);
for (unsigned int bank = 0; bank < config.NumberOfBanks; ++bank)
for (unsigned int bank = 0; bank < config.memSpec.NumberOfBanks; ++bank)
{
ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank));
if (lastCommand.isValidCommand())
{
if (lastCommand.getCommand() == Command::Read)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tRTP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tRTP);
}
else if (lastCommand.getCommand() == Command::ReadA)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tRTP + config.Timings.tRP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tRTP + config.memSpec.tRP);
}
else if (lastCommand.getCommand() == Command::Write)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
}
else if(lastCommand.getCommand() == Command::WriteA)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR + config.Timings.tRP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + config.memSpec.tRP);
}
else if (lastCommand.getCommand() == Command::AutoRefresh)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tRFC);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tRFC);
}
else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tXP);
}
else if (lastCommand.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommand.getEnd(), config.Timings.tXSR);
command.delayToMeetConstraint(lastCommand.getEnd(), config.memSpec.tXSR);
}
else
reportFatal("Precharge All Checker",
@@ -56,7 +56,7 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c
ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank());
if (lastActivate.isValidCommand())
{
command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS);
command.delayToMeetConstraint(lastActivate.getStart(), config.memSpec.tRAS);
}
state.bus.moveCommandToNextFreeSlot(command);

8
dram/src/controller/core/scheduling/checker/PrechargeChecker.cpp
View File

@@ -21,15 +21,15 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
{
if (lastCommand.getCommand() == Command::Read)
{
command.delayToMeetConstraint(lastCommand.getStart(),config.Timings.tRTP);
command.delayToMeetConstraint(lastCommand.getStart(),config.memSpec.tRTP);
}
else if (lastCommand.getCommand() == Command::Write)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR);
}
else if (lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tXP);
}
else
reportFatal("Precharge Checker", "Precharge can not follow " + commandToString(lastCommand.getCommand()));
@@ -38,7 +38,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank());
if (lastActivate.isValidCommand())
{
command.delayToMeetConstraint(lastActivate.getStart(), config.Timings.tRAS);
command.delayToMeetConstraint(lastActivate.getStart(), config.memSpec.tRAS);
}

12
dram/src/controller/core/scheduling/checker/ReadChecker.cpp
View File

@@ -24,7 +24,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommand.getCommand() == Command::Activate)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tRCD);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tRCD);
}
else if (lastCommand.getCommand() == Command::Read)
{
@@ -36,7 +36,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
}
else if (lastCommand.getCommand() == Command::PDNPX || lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tXP);
}
else
reportFatal("Read Checker", "Read can not follow " + commandToString(lastCommand.getCommand()));
@@ -44,7 +44,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command))
{
command.delayStart(config.Timings.clk);
command.delayStart(config.memSpec.clk);
}
}
@@ -84,7 +84,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand& read) const
{
ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank());
if (lastSREFX.isValidCommand())
read.delayToMeetConstraint(lastSREFX.getStart(), config.Timings.tXSRDLL);
read.delayToMeetConstraint(lastSREFX.getStart(), config.memSpec.tXSRDLL);
}
sc_time ReadChecker::readToRead(ScheduledCommand& firstRead, ScheduledCommand& secondRead)
@@ -92,7 +92,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand& firstRead, ScheduledCommand& s
sc_assert(firstRead.getCommand() == Command::Read || firstRead.getCommand() == Command::ReadA);
sc_assert(secondRead.getCommand() == Command::Read || secondRead.getCommand() == Command::ReadA);
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? config.tCCD_L : config.tCCD_S;
return max(tCCD, getReadAccessTime());
}
@@ -102,7 +102,7 @@ sc_time ReadChecker::writeToRead(ScheduledCommand& write, ScheduledCommand& read
sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA);
sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA);
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config.tWTR_L : config.tWTR_S;
return config.tWL + getWriteAccessTime() + tWTR;
}

10
dram/src/controller/core/scheduling/checker/RefreshChecker.cpp
View File

@@ -21,24 +21,24 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommandOnBank.getCommand() == Command::Precharge || lastCommandOnBank.getCommand() == Command::PrechargeAll)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::ReadA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tRTP + config.Timings.tRP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tRTP + config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::WriteA)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(),
config.Timings.tWL + getWriteAccessTime() + config.Timings.tWR + config.Timings.tRP);
config.memSpec.tWL + getWriteAccessTime() + config.memSpec.tWR + config.memSpec.tRP);
}
else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXP);
}
else if (lastCommandOnBank.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.Timings.tXSR);
command.delayToMeetConstraint(lastCommandOnBank.getStart(), config.memSpec.tXSR);
}
else if (lastCommandOnBank.getCommand() == Command::AutoRefresh)
{

10
dram/src/controller/core/scheduling/checker/WriteChecker.cpp
View File

@@ -22,7 +22,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommand.getCommand() == Command::Activate)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tRCD);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tRCD);
}
else if (lastCommand.getCommand() == Command::Read)
{
@@ -34,7 +34,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
}
else if (lastCommand.getCommand() == Command::PDNPX || lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getStart(), config.Timings.tXP);
command.delayToMeetConstraint(lastCommand.getStart(), config.memSpec.tXP);
}
else
reportFatal("Write Checker", "Write can not follow " + commandToString(lastCommand.getCommand()));
@@ -42,7 +42,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command))
{
command.delayStart(config.Timings.clk);
command.delayStart(config.memSpec.clk);
}
}
@@ -83,7 +83,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand& firstWrite, ScheduledComman
sc_assert(firstWrite.getCommand() == Command::Write || firstWrite.getCommand() == Command::WriteA);
sc_assert(secondWrite.getCommand() == Command::Write || secondWrite.getCommand() == Command::WriteA);
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? config.tCCD_L : config.tCCD_S;
return max(tCCD, getWriteAccessTime());
}
@@ -93,7 +93,7 @@ sc_time WriteChecker::readToWrite(ScheduledCommand& read, ScheduledCommand& writ
sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA);
sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA);
TimingConfiguration& config = Configuration::getInstance().Timings;
MemSpec& config = Configuration::getInstance().memSpec;
return config.tRL + getReadAccessTime() - config.tWL + config.clk * 2;
}

2
dram/src/simulation/Dram.h
View File

@@ -70,7 +70,7 @@ struct Dram: sc_module
TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().memSpec.clk.value();
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
if (phase == BEGIN_PRE)

2
dram/src/simulation/Simulation.cpp
View File

@@ -128,7 +128,7 @@ void Simulation::start()
report("\n\nStarting simulation:");
report(headline);
report(" -> setup: \t\t" + getFileName(traceName));
report(" -> memspec: \t\t" + Configuration::getInstance().MemoryId);
report(" -> memspec: \t\t" + Configuration::getInstance().memSpec.MemoryId);
report(" -> transactions: \t" + to_string(totalTransactions));
cout << endl;
simulationStartTime = clock();

4
dram/src/simulation/TracePlayer.h
View File

@@ -64,11 +64,11 @@ TracePlayer<BUSWIDTH>::TracePlayer(sc_module_name, string pathToTrace, unsigned
SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str());
if(clkMhz == 0)
clk = core::Configuration::getInstance().Timings.clk;
clk = core::Configuration::getInstance().memSpec.clk;
else
clk = core::FrequencyToClk(clkMhz);
this->burstlenght = core::Configuration::getInstance().BurstLength;
this->burstlenght = core::Configuration::getInstance().memSpec.BurstLength;
iSocket.register_nb_transport_bw(this, &TracePlayer<BUSWIDTH>::nb_transport_bw);
}