93 lines
2.6 KiB
C++
93 lines
2.6 KiB
C++
/*
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* MemSpec.h
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*
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* Created on: Mar 6, 2014
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* Author: jonny
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*/
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#ifndef MemSpec_H_
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#define MemSpec_H_
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#include <systemc.h>
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#include <map>
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#include "../../../common/dramExtension.h"
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namespace core{
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struct RefreshTiming
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{
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RefreshTiming() {}
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RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
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sc_time tRFC;
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sc_time tREFI;
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};
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struct MemSpec
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{
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MemSpec()
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{
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//default DDR4
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}
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const std::vector<Bank>& getBanks() const
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{
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static std::vector<Bank> banks;
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if (banks.size() == 0)
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{
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for (unsigned int i = 0; i < NumberOfBanks; i++)
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{
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banks.push_back(Bank(i));
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}
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}
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return banks;
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}
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std::string MemoryId = "not defined.";
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std::string MemoryType = "not defined.";
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unsigned int NumberOfBanks;
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unsigned int NumberOfBankGroups;
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unsigned int BurstLength;
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unsigned int nActivate;
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unsigned int DataRate;
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unsigned int NumberOfRows;
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sc_time clk;
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sc_time tRP; //precharge-time (pre -> act same bank)
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sc_time tRAS; //active-time (act -> pre same bank)
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sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
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sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd
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sc_time tCCD_L;
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sc_time tRTP; //Read to precharge
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sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group)
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sc_time tRRD_L; //.. (same bank group)
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sc_time tRCD; //act -> read/write
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sc_time tNAW; //n activate window
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sc_time tRL; //read latency (read command start to data strobe)
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sc_time tWL; //write latency
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sc_time tWR; //write recovery (write to precharge)
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sc_time tWTR_S; //write to read (different bank group)
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sc_time tWTR_L; //.. (same bank group)
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sc_time tCKESR; //min time in sref
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sc_time tCKE; //min time in pdna or pdnp
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sc_time tXP; //min delay to row access command after pdnpx pdnax
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sc_time tXPDLL; //min delay to row access command after pdnpx pdnax for dll commands
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sc_time tXSR; //min delay to row access command after srefx
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sc_time tXSRDLL; //min delay to row access command after srefx for dll commands
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sc_time tAL; //additive delay (delayed execution in dram)
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sc_time tRFC; //min ref->act delay
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sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI
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std::map<Bank, RefreshTiming> refreshTimings;//ensure that map is populated completely in memspecloader
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//act and read/write commands remain for this timespan in history
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sc_time tActHistory(){return tNAW;}
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sc_time tDataStrobeHistory(){return tWTR_L;}
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};
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} /* namespace core */
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#endif /* MemSpec_H_ */
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