Lukas Steiner (2)
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ed96f9fb54
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Added new CheckerDDR3, changed checker type in controller to CheckerIF for polymorphism.
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2019-07-30 16:25:05 +02:00 |
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Lukas Steiner (2)
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1053f7c1b7
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Created CheckerIF, removed old CheckerDDR3.
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2019-07-30 16:03:49 +02:00 |
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Lukas Steiner (2)
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b9f0c31ddf
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Moved controller state into timing checker. Inserted preambles.
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2019-07-30 15:14:24 +02:00 |
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Lukas Steiner (2)
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b477424a98
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Bugfix: Commands on one bank can overlap now.
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2019-07-30 13:30:59 +02:00 |
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Lukas Steiner
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fb9abb9cee
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Changed type of payloadID to uint64_t for overflow prevention.
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2019-07-29 20:55:40 +02:00 |
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Lukas Steiner (2)
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4fa59c2410
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Included ControllerRecordable for disabling of trace recording.
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2019-07-29 16:44:14 +02:00 |
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Lukas Steiner (2)
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91755962a2
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Improvement in timing checker: additional map instead of for loops.
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2019-07-29 14:17:03 +02:00 |
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Lukas Steiner (2)
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de650810dd
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Changed interface of scheduler, small bugfix (wrong debug message in Controller).
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2019-07-29 11:05:03 +02:00 |
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Lukas Steiner
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dbcdf3f61d
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Included FAW check.
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2019-07-28 22:53:27 +02:00 |
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Lukas Steiner
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42344ce87f
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Removed lastDataStrobeCommands in ControllerState, removed unused methods in timing checker.
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2019-07-28 21:50:28 +02:00 |
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Lukas Steiner
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a05b0ed610
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Removed RowBufferState in ControllerState.
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2019-07-28 20:57:48 +02:00 |
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Lukas Steiner
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e0743b71d6
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Small improvement in ControllerNew (redundant event triggers), renaming in ControllerState.
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2019-07-28 20:45:03 +02:00 |
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Lukas Steiner
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733525e787
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Included command mux which selects the oldest payload and a command mux interface.
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2019-07-27 21:12:22 +02:00 |
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Lukas Steiner
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215790a931
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Created different schedulers (Fifo and FrFcfs) and a scheduler interface.
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2019-07-27 19:24:09 +02:00 |
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Lukas Steiner (2)
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c4c2640594
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Moved event trigger out of BankMachine.
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2019-07-26 16:28:22 +02:00 |
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Lukas Steiner (2)
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3f913b5c16
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Arbiter now assigns each payload an ID for transaction order decision in CommandMux.
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2019-07-26 15:48:58 +02:00 |
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Lukas Steiner (2)
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f2ab2fe3ee
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Included first test for CommandMux.
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2019-07-25 16:40:03 +02:00 |
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Lukas Steiner (2)
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38a21088a0
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Merge branch 'master' into DRAMSys4.0_ctrl
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2019-07-25 13:47:57 +02:00 |
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Matthias Jung
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7304055a22
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Merge branch 'googletest_merge2' into 'master'
Include googletest and subproject for unit tests.
See merge request ems/astdm/dram.sys!240
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2019-07-25 12:02:33 +02:00 |
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Lukas Steiner (2)
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a303f242e6
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Included googletest and subproject for unit tests.
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2019-07-25 11:49:18 +02:00 |
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Lukas Steiner
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7bd0950e1e
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Some minor changes.
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2019-07-23 21:30:29 +02:00 |
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Lukas Steiner (2)
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e1e53b5c2e
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Moved parts of logic from CommandMux::selectCommand to controlMethod, moved commandFinishedTime from BMs to Controller.
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2019-07-23 16:20:38 +02:00 |
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Lukas Steiner (2)
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1e8b8e37ea
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Moved if statements from inner methods to controllerMethod().
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2019-07-23 15:10:19 +02:00 |
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Lukas Steiner (2)
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e7552f6916
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Code cleanup.
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2019-07-23 14:30:01 +02:00 |
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Lukas Steiner (2)
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0d0c7415b2
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Fixed clk cycle waiting for fifo strict transaction order.
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2019-07-23 14:13:51 +02:00 |
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Lukas Steiner
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6aa2533edd
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New controller is working.
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2019-07-22 20:31:17 +02:00 |
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Lukas Steiner
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f69771e7be
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Simulation is running to the end, results may still be wrong.
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2019-07-22 17:59:51 +02:00 |
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Lukas Steiner
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1ce8996ece
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Some bugs are fixed, still not running.
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2019-07-22 01:53:18 +02:00 |
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Lukas Steiner
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ef011ad52c
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Ready for debugging.
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2019-07-22 00:23:12 +02:00 |
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Lukas Steiner
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9204a88a28
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Included some functionality, included scheduler.
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2019-07-20 23:32:37 +02:00 |
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Lukas Steiner (2)
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cd5b5cb423
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Included new controller classes.
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2019-07-20 15:53:30 +02:00 |
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Lukas Steiner (2)
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41e2db0b5a
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Removed refresh and power down.
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2019-07-19 10:29:14 +02:00 |
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Lukas Steiner (2)
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f43ea71e95
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Minor changes in new timing checker.
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2019-07-16 15:52:02 +02:00 |
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Lukas Steiner (2)
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be83ad01cb
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Included remaining commands.
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2019-07-11 15:22:09 +02:00 |
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Lukas Steiner (2)
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9be64edaa9
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Added commands ACT, PRE, PREA, RD, RDA, WR, WRA, PDEA, PDEP to new timing checker.
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2019-07-10 15:55:45 +02:00 |
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Lukas Steiner (2)
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3e4e8e9408
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Included new timing checker for DDR3.
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2019-07-09 15:52:09 +02:00 |
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Lukas Steiner (2)
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cb393b8abf
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Renaming of commands, TODOs in timing checkers.
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2019-07-05 16:17:52 +02:00 |
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Lukas Steiner (2)
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37b2dc9e4d
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Renaming of commands according to DRAMml.
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2019-07-04 10:13:19 +02:00 |
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Lukas Steiner (2)
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34626448bb
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RefMode (tRFC) is now only configurable during initialization.
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2019-07-02 16:25:43 +02:00 |
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Lukas Steiner (2)
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41cc447d86
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Included timing parameters for RGR.
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2019-07-02 14:25:53 +02:00 |
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Lukas Steiner (2)
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ffdc67945a
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Removed specific DRAMPower configuration in DRAMs.
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2019-07-01 15:00:01 +02:00 |
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Lukas Steiner (2)
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50f90176a0
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Included specific timing parameters for different DRAMs.
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2019-07-01 11:16:36 +02:00 |
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Lukas Steiner (2)
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3b509a7c17
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Marked old timing parameters with "_old" for inclusion of new ones without conflicts.
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2019-07-01 10:23:30 +02:00 |
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Lukas Steiner
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9b8729c58b
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Bugfix: nbrOfRanks is only part of some memspecs for WideIO.
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2019-06-28 17:53:52 +02:00 |
|
Lukas Steiner
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409e49f044
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Bugfix: call loadCommons() only after creating a memSpec object.
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2019-06-28 17:36:51 +02:00 |
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Lukas Steiner (2)
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21adf2ac70
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Moved some timings to loadCommons().
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2019-06-28 16:26:46 +02:00 |
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Lukas Steiner (2)
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a5fb1327a1
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Renaming of timings.
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2019-06-28 15:14:47 +02:00 |
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Lukas Steiner (2)
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7da2aacfa3
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Separate constructors for each DRAM type.
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2019-06-28 14:40:07 +02:00 |
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Lukas Steiner (2)
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72152bca8b
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Included GenericController for later verilator inclusion.
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2019-06-28 14:10:09 +02:00 |
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Lukas Steiner (2)
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ac4e4c7783
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Moved specific timing calculation functions to MemSpecs.
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2019-06-27 16:02:24 +02:00 |
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