12bfba1fb3
Fix various bugs
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- Fix data race for some tests by disabling database recording
- Fix undefined behaviour in configuration test
- Port clkMhz to tCK for simulation script
- Port memUtil Python script to tCK with backwards compatibility
2024-02-26 09:58:19 +01:00
454cb00ddb
Refactor: remove monolithic configuration class
2024-02-23 11:54:51 +01:00
Lukas Steiner
0b88161640
Merge branch 'DramCleanup' into 'develop'
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Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files
See merge request ems/astdm/modeling.dram/dram.sys.5!58
2023-11-16 13:25:16 +00:00
6645a9ed54
Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files
2023-11-14 14:57:25 +01:00
3481703e6e
Fix a bug where plotting failed with more than 1 thread
2023-11-07 09:50:10 +01:00
Lukas Steiner
5226b87a78
Merge branch 'fix_pyhton_scripts' into 'develop'
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Numerous fixes for Python scripts
See merge request ems/astdm/modeling.dram/dram.sys.5!52
2023-10-20 07:52:26 +00:00
d2761ce060
Numerous fixes for Python scripts
2023-10-12 11:58:18 +02:00
d2e5bd36de
Fix all warnings
2023-09-22 10:45:23 +02:00
Lukas Steiner
8224e97abe
Reformat all files.
2023-09-21 16:50:59 +02:00
f518ba883f
Fix PseudoChannel issue in TA
2023-09-21 09:22:28 +02:00
c07d09f392
Format all files
2023-08-29 09:26:25 +02:00
Lukas Steiner
12f2b73cde
Additional check of byte enable pointer.
2023-08-23 15:21:53 +02:00
Lukas Steiner
76e58b1755
Fix renaming.
2023-08-23 13:50:10 +02:00
Lukas Steiner
0f824e8b92
Do not allow masked write in default case.
2023-08-23 11:41:58 +02:00
Lukas Steiner
8c248e8e23
Remove masked write checks for HBM3.
2023-08-23 10:40:41 +02:00
a539e3c011
Merge branch 'develop' into work/partial_writes
2023-08-23 09:31:42 +02:00
4548d20b6e
Rename requiresMaskedWrite to requiresReadModifyWrite
2023-08-21 10:55:41 +02:00
c0f1b2f6a3
Add check to prevent masked writes in HBM3
2023-08-21 10:52:44 +02:00
a0f93a75e2
Merge develop
2023-08-21 10:01:08 +02:00
b3937cf63a
Add LPDDR5 Partial Write Support
2023-08-16 11:42:39 +02:00
09275bb789
Add support for MWR and MWRA to TraceAnalyzer
2023-08-16 09:38:57 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
40dbc518b6
Add hack in TimingCheckers to convert MWR to WR in insertion stage
2023-08-16 09:38:54 +02:00
f7066a22b0
First implementation of Partial Writes
2023-08-16 09:38:54 +02:00
Lukas Steiner
a8d15e35a5
Merge branch 'work/regression_tests' into 'develop'
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Add a regression test for every standard
See merge request ems/astdm/modeling.dram/dram.sys.5!34
2023-08-15 12:00:48 +00:00
Lukas Steiner
5598d53ebd
Merge branch 'cmake_debug' into 'develop'
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Disable CMake diagnostics print
See merge request ems/astdm/modeling.dram/dram.sys.5!40
2023-08-15 09:28:28 +00:00
81eaccf3d6
Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3
2023-08-15 10:58:10 +02:00
Lukas Steiner
56c9f5f5f0
Merge branch 'initialize_generalinfotable' into 'develop'
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Write GeneralInfo table at the beginning
See merge request ems/astdm/modeling.dram/dram.sys.5!39
2023-08-14 13:33:40 +00:00
Lukas Steiner
cb9689a08d
Merge branch 'work/simulator_library' into 'develop'
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Introduce Simulator class
See merge request ems/astdm/modeling.dram/dram.sys.5!35
2023-08-10 12:19:33 +00:00
ccc1bc73c4
Disable CMake diagnostics print
2023-08-09 14:57:29 +02:00
d392d0ab98
Write GeneralInfo table at the beginning
...
and do not include information in it that is only known at the end of
the simulation. These can trivially be calculated by the trace itself
and would be redundant information regardless.
The TraceAnalyzer gets the number of transactions and the length of
the trace by additional SQL queries.
This enables us to inspect traces of simulations that were aborted
without finishing cleanlywithout finishing cleanly.
2023-08-09 11:55:10 +02:00
14ecc64ed0
Introduce Simulator class
2023-07-14 14:31:03 +02:00
Lukas Steiner
cacbf59d96
Missing refactoring.
2023-06-30 16:04:23 +02:00
Lukas Steiner
12dcbfd917
Use scoped enums for DRAM types.
2023-06-30 15:49:41 +02:00
Lukas Steiner
ba3f367676
Use type safe index vectors in timing checkers (2/2).
2023-06-21 12:59:26 +02:00
Lukas Steiner
72f3d04189
Fix bug in checker, remove redundant checks.
2023-06-16 13:42:14 +02:00
093ee73d54
Add .clang-tidy and .clang-format configurations
2023-06-09 11:29:35 +02:00
a9759f51fa
Enable warnings in dev preset and fix them
2023-06-09 11:29:15 +02:00
Lukas Steiner
6f7ca94d27
Move pct files to scripts folder.
2023-05-26 15:48:21 +02:00
Lukas Steiner
71172f9545
Remove old files, move pct to extensions.
2023-05-26 15:39:06 +02:00
Lukas Steiner
20f6aae787
Replace tabs with whitespaces.
2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02
Update TUK to RPTU.
2023-05-25 15:15:52 +02:00
Lukas Steiner
ea40721ac0
Merge branch 'work/namespacing' into 'develop'
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Namespace the complete DRAMSys library
See merge request ems/astdm/modeling.dram/dram.sys.5!21
2023-05-23 12:31:44 +00:00
Lukas Steiner
fdb51f71ec
Merge branch 'work/pybind' into 'develop'
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Switch to pybind11 in TraceAnalyzer
See merge request ems/astdm/modeling.dram/dram.sys.5!19
2023-05-23 12:24:11 +00:00
Lukas Steiner
43706ca930
Build Trace Analyzer by default if extensions are enabled.
2023-05-23 12:11:39 +00:00
69cd04c448
Namespace the complete DRAMSys library
2023-05-17 11:42:00 +02:00
edd52e0fe1
Switch to pybind11
...
With the switch to pybind11, the complexity of the Python integration
in the TraceAnalyzer can be greatly reduced. The new code is much
easier to understand and fixes a number of bugs regarding the Python
integration.
2023-05-17 11:41:44 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
Lukas Steiner
9a1443835d
Merge branch 'develop' into wip/unit_test_preps
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# Conflicts:
# extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
2023-04-14 11:35:32 +02:00
Lukas Steiner
9b31fef555
Use local copies of sc_max_time() instead of calling the function.
2023-04-14 10:03:59 +02:00
