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Enable warnings in dev preset and fix them

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This commit is contained in:
Derek Christ
2023-05-16 09:44:42 +02:00
parent ad96e3ba14
commit a9759f51fa
67 changed files with 172 additions and 166 deletions
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16
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -59,30 +59,30 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")),
tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")),
//tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
//tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
//tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
//tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
//tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
//tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
//tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
@@ -104,10 +104,10 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")),
tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
tBURST16(tCK * 16 / dataRate),
tBURST32(tCK * 32 / dataRate),
bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B))
bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset"))
{
commandLengthInCycles[Command::ACT] = 2;