diff --git a/CMakePresets.json b/CMakePresets.json index 6acf65ad..3bd3c6fc 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -69,7 +69,8 @@ "std" ], "cacheVariables": { - "CMAKE_BUILD_TYPE": "Debug" + "CMAKE_BUILD_TYPE": "Debug", + "CMAKE_CXX_FLAGS": "-Wall -Wextra -Wpedantic" } } ] diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index a34d70ba..55063551 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -59,30 +59,30 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")), tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), tRL (tCK * memSpec.memtimingspec.entries.at("RL")), + //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), + tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), //tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), //tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), tWL (tCK * memSpec.memtimingspec.entries.at("WL")), + tWR (tCK * memSpec.memtimingspec.entries.at("WR")), //tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), //tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), //tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), //tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), //tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), @@ -104,10 +104,10 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), tBURST16(tCK * 16 / dataRate), tBURST32(tCK * 32 / dataRate), - bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)) + bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { commandLengthInCycles[Command::ACT] = 2; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 17bfcbd3..6a4a8d04 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -89,6 +89,7 @@ public: void finalize(); private: + std::string name; const Configuration& config; const MemSpec& memSpec; @@ -131,8 +132,6 @@ private: std::vector recordedPhases; }; - std::string name; - std::string mcconfig, memspec, traces; void prepareSqlStatements(); diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 34c479da..44745262 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -299,10 +299,7 @@ public: return new EccExtension; } - void copy_from(tlm_extension_base const &ext) override - { - auto const &cpyFrom = dynamic_cast(ext); - } + void copy_from([[maybe_unused]] tlm_extension_base const & ext) override {} }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index 1f3de24b..3cc9de21 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -61,7 +61,7 @@ public: [[nodiscard]] bool intersects(const TimeInterval &other) const; }; -constexpr const char headline[] = +constexpr const std::string_view headline = "==========================================================================="; std::string getPhaseName(const tlm::tlm_phase &phase); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 75979552..25706279 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -102,8 +102,8 @@ public: [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - [[nodiscard]] sc_core::sc_time getCommandLength(Command /*command*/) const; - [[nodiscard]] double getCommandLengthInCycles(Command /*command*/) const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const; + [[nodiscard]] double getCommandLengthInCycles(Command command) const; [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index a46cb218..9aeff6b5 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -61,7 +61,6 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,16 +70,17 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), + tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), @@ -127,7 +127,7 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -156,7 +156,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 8e86697b..cae2ed1e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -146,7 +146,7 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -174,7 +174,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 62c38281..a8999f80 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 88fac485..f536f8b9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 94fb972b..23fae0c4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -60,7 +60,6 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), @@ -96,7 +95,8 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")), tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")), tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; @@ -175,7 +175,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 431ae424..dc4a3700 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -163,7 +163,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index a1b1fe1f..fa59ff5b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -62,12 +62,12 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), @@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb + tCK; @@ -166,7 +166,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index e2d7aa2d..41b93a5a 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -61,7 +61,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,14 +70,15 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), + tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) @@ -104,7 +104,7 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -129,7 +129,7 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl return SC_ZERO_TIME; } -TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index f78bd97e..0912ef88 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -60,8 +60,6 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfDevices")), tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tAC (tCK * memSpec.memtimingspec.entries.at("AC")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -70,11 +68,13 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), - tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tAC (tCK * memSpec.memtimingspec.entries.at("AC")), + tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), + tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), @@ -133,7 +133,7 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -161,7 +161,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index fd193b81..e4d78e94 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb; @@ -151,7 +151,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl throw; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 3774430c..fb74fe6d 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -45,7 +45,7 @@ namespace DRAMSys { BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : scheduler(scheduler), memSpec(*config.memSpec), bank(bank), + : memSpec(*config.memSpec), scheduler(scheduler), bank(bank), bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)), refreshManagement(config.refreshManagement) {} diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 39a04f2b..39da86db 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -53,7 +53,7 @@ class BankMachine : public ManagerIF { public: CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override; + void update(Command command) override; void block(); [[nodiscard]] Rank getRank() const; diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 4e43523d..c6f520c5 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -84,7 +84,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 26 DECLARE_EXTENDED_PHASE(END_SREF); // 27 #ifdef DRAMPOWER -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase /*phase*/ /*phase*/); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); #endif bool phaseHasDataStrobe(tlm::tlm_phase phase); diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index dbc0f7c3..d689e6ab 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -80,10 +80,10 @@ namespace DRAMSys { Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : - ControllerIF(name, config), addressDecoder(addressDecoder), - thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), - phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw), - blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay), + ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), + thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), + phyDelayBw(config.phyDelayBw), blockingReadDelay(config.blockingReadDelay), + blockingWriteDelay(config.blockingWriteDelay), addressDecoder(addressDecoder), minBytesPerBurst(config.memSpec->defaultBytesPerBurst), maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { @@ -440,7 +440,9 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& /*trans*/,tlm_phase& /*phase*/, sc_time& /*delay*/) +tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index 16f86af0..d82ba70f 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -45,8 +45,8 @@ namespace DRAMSys ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), - activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing), - windowSizeTime(config.windowSize * memSpec.tCK) + windowSizeTime(config.windowSize * memSpec.tCK), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), + enableWindowing(config.enableWindowing) { if (enableWindowing) { @@ -65,8 +65,9 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload& /*trans*/, - tlm_phase& /*phase*/, sc_time& /*delay*/) +tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 99e95da6..06a8afaa 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -45,7 +45,7 @@ class ManagerIF public: virtual void evaluate() = 0; virtual CommandTuple::Type getNextCommand() = 0; - virtual void update(Command /*command*/) = 0; + virtual void update(Command command) = 0; virtual ~ManagerIF() = default; }; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index 996295e5..a3070f8c 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -44,7 +44,7 @@ class CmdMuxIF { public: virtual ~CmdMuxIF() = default; - virtual CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) = 0; + virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index c52ffdf0..6ff5772c 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF { public: explicit CmdMuxOldest(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; @@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF { public: explicit CmdMuxOldestRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index eb1b5b4a..2b98bc9e 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF { public: explicit CmdMuxStrict(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; @@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: explicit CmdMuxStrictRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index f874a198..8e81f472 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -50,7 +50,7 @@ public: void triggerInterruption() override {} CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override {} + void update([[maybe_unused]] Command command) override {} void evaluate() override {} }; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index 63bbc485..48d160cd 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -43,7 +43,7 @@ namespace DRAMSys { PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector& bankMachinesOnRank, - Rank rank, CheckerIF& checker) + Rank rank, [[maybe_unused]] CheckerIF& checker) : bankMachinesOnRank(bankMachinesOnRank) { setUpDummy(powerDownPayload, UINT64_MAX - 1, rank); diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index 5b9175d9..54cc6793 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -57,7 +57,7 @@ public: void triggerInterruption() override; CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override; + void update(Command command) override; void evaluate() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index 333ef9f1..de5fa193 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -46,8 +46,8 @@ namespace DRAMSys RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), - memSpec(*config.memSpec), maxPostponed(static_cast(config.refreshMaxPostponed)), + : memSpec(*config.memSpec), bankMachinesOnRank(bankMachinesOnRank), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed)), maxPulledin(-static_cast(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement) { timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(), diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 7ccd7ecd..0b287f03 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -58,7 +58,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 72328a5e..18c92d81 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF public: CommandTuple::Type getNextCommand() override; void evaluate() override {} - void update(Command /*command*/) override {} + void update([[maybe_unused]] Command command) override {} sc_core::sc_time getTimeForNextTrigger() override; private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index e1a90770..a4816f74 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank / 2)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank / 2)) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 88e7a489..548add98 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 8acc44eb..581e1d2f 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -45,7 +45,7 @@ namespace DRAMSys RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank)) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index 294b9412..fb955d99 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 802103c0..23eff9d9 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerGroup)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerGroup)), refreshManagement(config.refreshManagement) diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index 28b7d01d..70a98f99 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -59,7 +59,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index cce032be..f6a0f53a 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -48,7 +48,7 @@ namespace DRAMSys class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index ec95ee23..30a6c53b 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -44,7 +44,7 @@ namespace DRAMSys class RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) = 0; + virtual void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) = 0; virtual tlm::tlm_generic_payload* nextPayload() = 0; [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; virtual ~RespQueueIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index 4a355b17..cb698438 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -47,7 +47,7 @@ namespace DRAMSys class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 10df01b8..f590c32b 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -80,7 +80,7 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin return nullptr; } -bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { if (buffer[bank.ID()].size() >= 2) { @@ -91,7 +91,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co return false; } -bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFifo::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return buffer[bank.ID()].size() >= 2; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index 9bcb672d..7e922d93 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF public: explicit SchedulerFifo(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index f71f0f68..fa5e854a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -101,7 +101,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach return nullptr; } -bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; for (auto *it : buffer[bank.ID()]) @@ -116,7 +116,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) return false; } -bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return (buffer[bank.ID()].size() >= 2); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index e317b044..02215742 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF public: explicit SchedulerFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 6017dc28..fa285072 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -126,7 +126,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM return nullptr; } -bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; for (auto *it : buffer[bank.ID()]) @@ -141,7 +141,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman return false; } -bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return buffer[bank.ID()].size() >= 2; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 1f0536d7..282ecf5e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF public: explicit SchedulerFrFcfsGrp(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index 77e7e7ba..4be55fd3 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF public: explicit SchedulerGrpFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index bad6859a..085fef00 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -132,7 +132,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban return nullptr; } -bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm::tlm_command command) const { unsigned rowHitCounter = 0; if (!writeMode) @@ -161,7 +161,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command return false; } -bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm::tlm_command command) const { if (!writeMode) return (readBuffer[bank.ID()].size() >= 2); diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index fb4b2c2d..f9e6d207 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF public: explicit SchedulerGrpFrFcfsWm(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index f7b2577c..da3639b4 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -50,11 +50,11 @@ class SchedulerIF public: virtual ~SchedulerIF() = default; [[nodiscard]] virtual bool hasBufferSpace() const = 0; - virtual void storeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; - virtual void removeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; - [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const = 0; - [[nodiscard]] virtual bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const = 0; - [[nodiscard]] virtual bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const = 0; + virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0; + virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const = 0; + [[nodiscard]] virtual bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0; + [[nodiscard]] virtual bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const = 0; [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index 6517e8fa..f3a7e1c8 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -156,7 +156,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload, +tlm_sync_enum Arbiter::nb_transport_bw([[maybe_unused]] int id, tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + @@ -165,7 +165,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload, return TLM_ACCEPTED; } -void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) +void Arbiter::b_transport([[maybe_unused]] int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { trans.set_address(trans.get_address() - addressOffset); @@ -173,7 +173,7 @@ void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core:: iSocket[static_cast(decodedAddress.channel)]->b_transport(trans, delay); } -unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans) +unsigned int Arbiter::transport_dbg([[maybe_unused]] int id, tlm::tlm_generic_payload& trans) { trans.set_address(trans.get_address() - addressOffset); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index bc90e2c1..06ec9108 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,10 +87,10 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int /*id*/, tlm::tlm_generic_payload &payload, + tlm::tlm_sync_enum nb_transport_bw(int id, tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); - void b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); - unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); + void b_transport(int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); + unsigned int transport_dbg(int id, tlm::tlm_generic_payload& trans); const sc_core::sc_time tCK; const sc_core::sc_time arbitrationDelayFw; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index 6c318b48..8ebdd133 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -234,9 +234,9 @@ void DRAMSys::bindSockets() } } -void DRAMSys::report(const std::string& message) +void DRAMSys::report(std::string_view message) { - PRINTDEBUGMESSAGE(name(), message); + PRINTDEBUGMESSAGE(name(), message.data()); std::cout << message << std::endl; } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 0df0356b..a641ec9c 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -99,7 +99,7 @@ protected: std::unique_ptr addressDecoder; - void report(const std::string& message); + void report(std::string_view message); void bindSockets(); private: diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index c0a988eb..db604fe2 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -68,8 +68,8 @@ namespace DRAMSys Dram::Dram(const sc_module_name& name, const Configuration& config) - : sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode), - powerAnalysis(config.powerAnalysis), useMalloc(config.useMalloc) + : sc_module(name), memSpec(*config.memSpec), storeMode(config.storeMode), powerAnalysis(config.powerAnalysis), + useMalloc(config.useMalloc), tSocket("socket") { uint64_t channelSize = memSpec.getSimMemSizeInBytes() / memSpec.numberOfChannels; if (storeMode == Configuration::StoreMode::Store) @@ -202,7 +202,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans) return 0; } -void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay) +void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& delay) { static bool printedWarning = false; diff --git a/src/simulator/simulator/EccModule.cpp b/src/simulator/simulator/EccModule.cpp index cf1a25d0..5933d969 100644 --- a/src/simulator/simulator/EccModule.cpp +++ b/src/simulator/simulator/EccModule.cpp @@ -46,8 +46,8 @@ using namespace tlm; EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder) : sc_core::sc_module(name), payloadEventQueue(this, &EccModule::peqCallback), - addressDecoder(addressDecoder), - memoryManager(false) + memoryManager(false), + addressDecoder(addressDecoder) { iSocket.register_nb_transport_bw(this, &EccModule::nb_transport_bw); tSocket.register_nb_transport_fw(this, &EccModule::nb_transport_fw); @@ -94,12 +94,11 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ // Update the original address to account for the offsets cbPayload.set_address(addressDecoder.encodeAddress(decodedAddress)); - auto currentBlock = alignToBlock(decodedAddress.column); - // In case there is no entry yet. activeEccBlocks.try_emplace(decodedAddress.bank); #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = &cbPayload; @@ -160,8 +159,10 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); - auto currentBlock = alignToBlock(decodedAddress.column); + #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); + if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = pendingRequest; diff --git a/src/simulator/simulator/generator/RandomProducer.cpp b/src/simulator/simulator/generator/RandomProducer.cpp index b6a7001e..fafa99e9 100644 --- a/src/simulator/simulator/generator/RandomProducer.cpp +++ b/src/simulator/simulator/generator/RandomProducer.cpp @@ -48,10 +48,10 @@ RandomProducer::RandomProducer(uint64_t numRequests, : numberOfRequests(numRequests), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), generatorPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), dataLength(dataLength), dataAlignment(dataAlignment), + randomGenerator(this->seed), randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS), maxAddress.value_or((memorySize) - dataLength)) { diff --git a/src/simulator/simulator/generator/SequentialProducer.cpp b/src/simulator/simulator/generator/SequentialProducer.cpp index b39a6479..481b1808 100644 --- a/src/simulator/simulator/generator/SequentialProducer.cpp +++ b/src/simulator/simulator/generator/SequentialProducer.cpp @@ -51,9 +51,9 @@ SequentialProducer::SequentialProducer(uint64_t numRequests, maxAddress(maxAddress.value_or(memorySize - 1)), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), generatorPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), - dataLength(dataLength) + dataLength(dataLength), + randomGenerator(this->seed) { if (minAddress > memorySize - 1) SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); diff --git a/src/simulator/simulator/generator/TrafficGenerator.cpp b/src/simulator/simulator/generator/TrafficGenerator.cpp index 644f57b3..3fc99b3d 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.cpp +++ b/src/simulator/simulator/generator/TrafficGenerator.cpp @@ -41,15 +41,15 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator) - : consumer( + : stateTransistions(config.transitions), + consumer( config.name.c_str(), memoryManager, config.maxPendingReadRequests, config.maxPendingWriteRequests, [this] { return nextRequest(); }, std::move(transactionFinished), - std::move(terminateInitiator)), - stateTransistions(config.transitions) + std::move(terminateInitiator)) { unsigned int dataLength = config.dataLength.value_or(defaultDataLength); unsigned int dataAlignment = config.dataAlignment.value_or(dataLength); @@ -163,7 +163,7 @@ Request TrafficGenerator::nextRequest() auto newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; auto idleStateIt = idleStateClks.find(newState.value()); while (idleStateIt != idleStateClks.cend()) @@ -172,7 +172,7 @@ Request TrafficGenerator::nextRequest() newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; currentState = newState.value(); idleStateIt = idleStateClks.find(newState.value()); diff --git a/src/simulator/simulator/hammer/RowHammer.cpp b/src/simulator/simulator/hammer/RowHammer.cpp index 4ca7d7b3..fe76f357 100644 --- a/src/simulator/simulator/hammer/RowHammer.cpp +++ b/src/simulator/simulator/hammer/RowHammer.cpp @@ -49,7 +49,7 @@ RowHammer::RowHammer(uint64_t numRequests, Request RowHammer::nextRequest() { if (generatedRequests >= numberOfRequests) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; generatedRequests++; diff --git a/src/simulator/simulator/player/StlPlayer.cpp b/src/simulator/simulator/player/StlPlayer.cpp index d80a6157..3139cea9 100644 --- a/src/simulator/simulator/player/StlPlayer.cpp +++ b/src/simulator/simulator/player/StlPlayer.cpp @@ -47,15 +47,15 @@ StlPlayer::StlPlayer(std::string_view tracePath, unsigned int defaultDataLength, TraceType traceType, bool storageEnabled) - : traceFile(tracePath.data()), + : traceType(traceType), + storageEnabled(storageEnabled), playerPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), defaultDataLength(defaultDataLength), - traceType(traceType), - storageEnabled(storageEnabled), + traceFile(tracePath.data()), lineBuffers( {std::make_shared>(), std::make_shared>()}), - readoutBuffer(lineBuffers.at(0)), - parseBuffer(lineBuffers.at(1)) + parseBuffer(lineBuffers.at(1)), + readoutBuffer(lineBuffers.at(0)) { readoutBuffer->reserve(LINE_BUFFER_SIZE); parseBuffer->reserve(LINE_BUFFER_SIZE); @@ -90,7 +90,7 @@ Request StlPlayer::nextRequest() parserThread.join(); // The file is read in completely. Nothing more to do. - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; } } diff --git a/src/simulator/simulator/request/Request.h b/src/simulator/simulator/request/Request.h index 730236ff..61eccb0f 100644 --- a/src/simulator/simulator/request/Request.h +++ b/src/simulator/simulator/request/Request.h @@ -48,6 +48,6 @@ struct Request } command; uint64_t address{}; std::size_t length{}; - sc_core::sc_time delay; - std::vector data; + sc_core::sc_time delay{}; + std::vector data{}; }; diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index 8ae4417f..84c808dc 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -43,13 +43,13 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name, std::function transactionFinished, std::function terminate) : sc_module(name), + payloadEventQueue(this, &RequestIssuer::peqCallback), memoryManager(memoryManager), maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests), - nextRequest(std::move(nextRequest)), transactionFinished(std::move(transactionFinished)), terminate(std::move(terminate)), - payloadEventQueue(this, &RequestIssuer::peqCallback) + nextRequest(std::move(nextRequest)) { SC_THREAD(sendNextRequest); iSocket.register_nb_transport_bw(this, &RequestIssuer::nb_transport_bw); @@ -79,9 +79,6 @@ void RequestIssuer::sendNextRequest() tlm::tlm_phase phase = tlm::BEGIN_REQ; sc_core::sc_time delay = request.delay; - if (request.address == 0x4000f000) - int x = 0; - if (transactionsSent == 0) delay = sc_core::SC_ZERO_TIME; diff --git a/tests/tests_configuration/test_configuration.cpp b/tests/tests_configuration/test_configuration.cpp index 52cd12df..6e3fa4e9 100644 --- a/tests/tests_configuration/test_configuration.cpp +++ b/tests/tests_configuration/test_configuration.cpp @@ -87,7 +87,15 @@ protected: PowerDownPolicyType::NoPowerDown, ArbiterType::Simple, 128, - {}}; + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt}; DRAMSys::Config::SimConfig simConfig{0, false, diff --git a/tests/tests_dramsys/AddressDecoderTests.cpp b/tests/tests_dramsys/AddressDecoderTests.cpp index 1c49af9e..29794c50 100644 --- a/tests/tests_dramsys/AddressDecoderTests.cpp +++ b/tests/tests_dramsys/AddressDecoderTests.cpp @@ -47,8 +47,8 @@ protected: addressMappingJson(nlohmann::json::parse(addressMappingJsonString).at("addressmapping")), memSpecJson(nlohmann::json::parse(memSpecJsonString).at("memspec")), addressMappingConfig(addressMappingJson.get()), - memSpec(memSpecConfig), memSpecConfig(memSpecJson.get()), + memSpec(memSpecConfig), addressDecoder(addressMappingConfig, memSpec) { } diff --git a/tests/tests_simulator/cache/TargetMemory.cpp b/tests/tests_simulator/cache/TargetMemory.cpp index adf1af0f..b3f30353 100644 --- a/tests/tests_simulator/cache/TargetMemory.cpp +++ b/tests/tests_simulator/cache/TargetMemory.cpp @@ -49,9 +49,9 @@ TargetMemory::TargetMemory(const sc_core::sc_module_name &name, : sc_core::sc_module(name), tSocket("tSocket"), bufferSize(bufferSize), - peq(this, &TargetMemory::peqCallback), acceptDelay(acceptDelay), - memoryLatency(memoryLatency) + memoryLatency(memoryLatency), + peq(this, &TargetMemory::peqCallback) { tSocket.register_nb_transport_fw(this, &TargetMemory::nb_transport_fw); @@ -155,7 +155,7 @@ void TargetMemory::sendEndRequest(tlm::tlm_generic_payload &trans) bw_phase = tlm::END_REQ; delay = acceptDelay; - tlm::tlm_sync_enum status = tSocket->nb_transport_bw(trans, bw_phase, delay); + tSocket->nb_transport_bw(trans, bw_phase, delay); // Queue internal event to mark beginning of response delay = delay + memoryLatency; // MEMORY Latency diff --git a/tests/tests_simulator/cache/TargetMemory.h b/tests/tests_simulator/cache/TargetMemory.h index 40af3915..ba526a6c 100644 --- a/tests/tests_simulator/cache/TargetMemory.h +++ b/tests/tests_simulator/cache/TargetMemory.h @@ -65,7 +65,7 @@ private: void printBuffer(int max, int n); - static constexpr std::size_t SIZE = static_cast(64 * 1024); + static constexpr std::size_t SIZE = static_cast(64 * 1024); static constexpr std::size_t DEFAULT_BUFFER_SIZE = 8; const std::size_t bufferSize;