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Apply default clang-tidy fixes

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This commit is contained in:
Derek Christ
2023-05-15 13:08:26 +02:00
parent 2d590fda0d
commit ad96e3ba14
23 changed files with 183 additions and 190 deletions
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22
src/configuration/DRAMSys/config/TraceSetup.h
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@@ -70,7 +70,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid
struct TracePlayer
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -81,10 +81,10 @@ NLOHMANN_JSONIFY_ALL_THINGS(
struct TrafficGeneratorActiveState
{
unsigned int id;
unsigned int id{};
uint64_t numRequests;
double rwRatio;
uint64_t numRequests{};
double rwRatio{};
AddressDistribution addressDistribution;
std::optional<uint64_t> addressIncrement;
std::optional<uint64_t> minAddress;
@@ -120,7 +120,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probabili
struct TrafficGenerator
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -130,8 +130,8 @@ struct TrafficGenerator
std::optional<unsigned> dataLength;
std::optional<unsigned> dataAlignment;
uint64_t numRequests;
double rwRatio;
uint64_t numRequests{};
double rwRatio{};
AddressDistribution addressDistribution;
std::optional<uint64_t> addressIncrement;
std::optional<uint64_t> minAddress;
@@ -156,7 +156,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator,
struct TrafficGeneratorStateMachine
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -183,13 +183,13 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine,
struct RowHammer
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
uint64_t numRequests;
uint64_t rowIncrement;
uint64_t numRequests{};
uint64_t rowIncrement{};
};
NLOHMANN_JSONIFY_ALL_THINGS(

21
src/libdramsys/DRAMSys/common/TlmRecorder.cpp
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@@ -52,18 +52,21 @@ using namespace tlm;
namespace DRAMSys
{
TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) :
name(name), config(config), memSpec(*config.memSpec),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
TlmRecorder::TlmRecorder(const std::string &name,
const Configuration &config,
const std::string &dbName) :
name(name),
config(config),
memSpec(*config.memSpec),
currentDataBuffer(&recordingDataBuffer.at(0)),
storageDataBuffer(&recordingDataBuffer.at(1)),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
{
currentDataBuffer = &recordingDataBuffer[0];
storageDataBuffer = &recordingDataBuffer[1];
currentDataBuffer->reserve(transactionCommitRate);
storageDataBuffer->reserve(transactionCommitRate);
openDB(dbName);
char *sErrMsg;
char *sErrMsg = nullptr;
sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg);
sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg);
sqlite3_exec(db, "PRAGMA main.locking_mode=EXCLUSIVE", nullptr, nullptr, &sErrMsg);
@@ -146,7 +149,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase
}
else if (isFixedCommandPhase(phase))
{
tlm_generic_payload* keyTrans;
tlm_generic_payload* keyTrans = nullptr;
if (ChildExtension::isChildTrans(trans))
{
keyTrans = &ChildExtension::getParentTrans(trans);
@@ -210,7 +213,7 @@ void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans)
{
totalNumTransactions++;
char commandChar;
char commandChar = 0;
tlm_command command = trans.get_command();
if (command == TLM_READ_COMMAND)
commandChar = 'R';

2
src/libdramsys/DRAMSys/common/dramExtensions.h
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@@ -301,7 +301,7 @@ public:
void copy_from(tlm_extension_base const &ext) override
{
auto const &cpyFrom = static_cast<EccExtension const &>(ext);
auto const &cpyFrom = dynamic_cast<EccExtension const &>(ext);
}
};

10
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -139,6 +139,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
return tRCDWR + tCK;
}
if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
@@ -166,13 +167,12 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
if (command == Command::WR || command == Command::WRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerDDR3::CheckerDDR3(const Configuration& config)
CheckerDDR3::CheckerDDR3(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecDDR3*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecDDR3 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerDDR4::CheckerDDR4(const Configuration& config)
CheckerDDR4::CheckerDDR4(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecDDR4*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecDDR4 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR5::CheckerGDDR5(const Configuration& config)
CheckerGDDR5::CheckerGDDR5(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR5*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR5 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR5X::CheckerGDDR5X(const Configuration& config)
CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR5X*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR5X *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR6::CheckerGDDR6(const Configuration& config)
CheckerGDDR6::CheckerGDDR6(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR6*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR6 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerHBM2::CheckerHBM2(const Configuration& config)
CheckerHBM2::CheckerHBM2(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecHBM2*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecHBM2 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerLPDDR4::CheckerLPDDR4(const Configuration& config)
CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecLPDDR4*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecLPDDR4 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config)
CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecSTTMRAM*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecSTTMRAM *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp
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@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerWideIO::CheckerWideIO(const Configuration& config)
CheckerWideIO::CheckerWideIO(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecWideIO*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecWideIO *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerWideIO2::CheckerWideIO2(const Configuration& config)
CheckerWideIO2::CheckerWideIO2(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecWideIO2*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecWideIO2 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen");

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand
{
auto result = readyCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -102,7 +102,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
auto resultCas = readyCasCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
{
auto result = readyCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -112,7 +112,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
auto resultCas = readyCasCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;

70
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp
View File

@@ -149,50 +149,50 @@ void RefreshManagerPer2Bank::evaluate()
}
return;
}
else // if (state == RmState::Pulledin)
// if (state == RmState::Pulledin)
bool allBankPairsBusy = true;
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end();
bankIt++)
{
bool allBankPairsBusy = true;
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++)
bool pairIsBusy = false;
for (const auto *pairIt : *bankIt)
{
bool pairIsBusy = false;
for (const auto* pairIt : *bankIt)
if (!pairIt->isIdle())
{
if (!pairIt->isIdle())
{
pairIsBusy = true;
break;
}
}
if (!pairIsBusy)
{
allBankPairsBusy = false;
currentIterator = bankIt;
pairIsBusy = true;
break;
}
}
if (allBankPairsBusy)
if (!pairIsBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalP2B();
return;
allBankPairsBusy = false;
currentIterator = bankIt;
break;
}
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto *it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
}
return;
}
if (allBankPairsBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalP2B();
return;
}
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto *it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
}
return;
}
}

55
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -121,37 +121,36 @@ void RefreshManagerPerBank::evaluate()
(*currentIterator)->block();
skipSelection = true;
}
}
return;
}
else // if (state == RmState::Pulledin)
{
bool allBanksBusy = true;
for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
{
if ((*it)->isIdle())
{
currentIterator = it;
allBanksBusy = false;
break;
}
}
if (allBanksBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalPB();
return;
}
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
nextCommand = Command::REFPB;
return;
}
// if (state == RmState::Pulledin)
bool allBanksBusy = true;
for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
{
if ((*it)->isIdle())
{
currentIterator = it;
allBanksBusy = false;
break;
}
}
if (allBanksBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalPB();
return;
}
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
nextCommand = Command::REFPB;
return;
}
}

79
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp
View File

@@ -107,26 +107,6 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM
// No read row hit found or bank precharged
return readBuffer[bankID].front();
}
if (!writeBuffer[bankID].empty())
{
if (bankMachine.isActivated())
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : writeBuffer[bankID])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No write row hit found or bank precharged
return writeBuffer[bankID].front();
}
else
return nullptr;
}
else
{
if (!writeBuffer[bankID].empty())
{
if (bankMachine.isActivated())
@@ -142,24 +122,40 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM
// No write row hit found or bank precharged
return writeBuffer[bankID].front();
}
if (!readBuffer[bankID].empty())
{
if (bankMachine.isActivated())
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : readBuffer[bankID])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No read row hit found or bank precharged
return readBuffer[bankID].front();
}
else
return nullptr;
return nullptr;
}
if (!writeBuffer[bankID].empty())
{
if (bankMachine.isActivated())
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : writeBuffer[bankID])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No write row hit found or bank precharged
return writeBuffer[bankID].front();
}
if (!readBuffer[bankID].empty())
{
if (bankMachine.isActivated())
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : readBuffer[bankID])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No read row hit found or bank precharged
return readBuffer[bankID].front();
}
return nullptr;
}
bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
@@ -180,7 +176,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman
return false;
}
for (auto it : writeBuffer[bank.ID()])
for (auto *it : writeBuffer[bank.ID()])
{
if (ControllerExtension::getRow(*it) == row)
{
@@ -198,10 +194,9 @@ bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const
{
return readBuffer[bank.ID()].size() >= 2;
}
else
{
return writeBuffer[bank.ID()].size() >= 2;
}
return writeBuffer[bank.ID()].size() >= 2;
}
const std::vector<unsigned>& SchedulerGrpFrFcfs::getBufferDepth() const

30
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp
View File

@@ -113,25 +113,23 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban
}
return nullptr;
}
else
if (!writeBuffer[bankID].empty())
{
if (!writeBuffer[bankID].empty())
if (bankMachine.isActivated())
{
if (bankMachine.isActivated())
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : writeBuffer[bankID])
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : writeBuffer[bankID])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
// No row hit found or bank precharged
return writeBuffer[bankID].front();
}
return nullptr;
// No row hit found or bank precharged
return writeBuffer[bankID].front();
}
return nullptr;
}
bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const
@@ -151,7 +149,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command
return false;
}
for (auto it : writeBuffer[bank.ID()])
for (auto *it : writeBuffer[bank.ID()])
{
if (ControllerExtension::getRow(*it) == row)
{
@@ -159,8 +157,8 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command
if (rowHitCounter == 2)
return true;
}
}
return false;
}
return false;
}
bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const

6
src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
View File

@@ -162,8 +162,7 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const
// Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit.
for (const auto &it : vXor)
{
uint64_t xoredBit;
xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it.first);
encAddr |= xoredBit << it.first;
}
@@ -207,8 +206,7 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const
// Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit.
for (const auto &it : vXor)
{
uint64_t xoredBit;
xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it.first);
encAddr |= xoredBit << it.first;
}

26
src/simulator/simulator/Cache.cpp
View File

@@ -123,8 +123,8 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase)
if (phase == HIT_HANDLING) // direct hit, account for the hit delay
{
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address());
hitQueue.emplace_back(index, tag, &trans);
@@ -134,8 +134,8 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase)
{
accessCacheAndSendResponse(trans);
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address());
auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(),
@@ -166,8 +166,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans)
{
if (hasBufferSpace())
{
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address());
auto mshrEntry =
@@ -290,8 +290,8 @@ bool Cache::isHit(index_t index, tag_t tag) const
bool Cache::isHit(uint64_t address) const
{
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(address);
return isHit(index, tag);
@@ -360,7 +360,7 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index)
// There are still entries in mshrQueue to the oldest line -> do not evict it
return nullptr;
}
else if (std::find_if(hitQueue.begin(), hitQueue.end(),
if (std::find_if(hitQueue.begin(), hitQueue.end(),
[index, oldestLine](const BufferEntry &entry)
{ return (index == entry.index) && (oldestLine.tag == entry.tag); }) != hitQueue.end())
{
@@ -413,8 +413,8 @@ void Cache::processMshrQueue()
// Note: This is the same address for all entries in the requests list
uint64_t alignedAddress = getAlignedAddress(mshrIt->requestList.front()->get_address());
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(alignedAddress);
// Search through the writeBuffer in reverse order to get the most recent entry.
@@ -515,8 +515,8 @@ void Cache::processWriteBuffer()
/// Fill allocated cache line with data from memory
void Cache::fillLine(tlm_generic_payload &trans)
{
index_t index;
tag_t tag;
index_t index = 0;
tag_t tag = 0;
std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address());
CacheLine &allocatedLine =

4
src/simulator/simulator/request/Request.h
View File

@@ -46,8 +46,8 @@ struct Request
Write,
Stop
} command;
uint64_t address;
std::size_t length;
uint64_t address{};
std::size_t length{};
sc_core::sc_time delay;
std::vector<unsigned char> data;
};