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Apply clang-tidy readability-named-parameter fixes

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This commit is contained in:
Derek Christ
2023-05-15 11:52:00 +02:00
parent 5d8d7c197e
commit 2d590fda0d
37 changed files with 73 additions and 73 deletions
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4
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -102,8 +102,8 @@ public:
[[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] sc_core::sc_time getCommandLength(Command) const;
[[nodiscard]] double getCommandLengthInCycles(Command) const;
[[nodiscard]] sc_core::sc_time getCommandLength(Command /*command*/) const;
[[nodiscard]] double getCommandLengthInCycles(Command /*command*/) const;
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
protected:

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
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@@ -127,7 +127,7 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
@@ -156,7 +156,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
throw;
}
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
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@@ -146,7 +146,7 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
@@ -174,7 +174,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
throw;
}
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
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@@ -162,7 +162,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
throw;
}
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -162,7 +162,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
throw;
}
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
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@@ -175,7 +175,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
throw;
}
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
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@@ -162,7 +162,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
throw;
}
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const
return tREFIpb;
}
sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB)
return tRPpb + tCK;
@@ -166,7 +166,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
throw;
}
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -104,7 +104,7 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
@@ -129,7 +129,7 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl
return SC_ZERO_TIME;
}
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -133,7 +133,7 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
@@ -161,7 +161,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
throw;
}
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tAC, tRL + tAC + burstDuration};

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::PREPB)
return tRPpb;
@@ -151,7 +151,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
throw;
}
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};

2
src/libdramsys/DRAMSys/controller/BankMachine.h
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@@ -53,7 +53,7 @@ class BankMachine : public ManagerIF
{
public:
CommandTuple::Type getNextCommand() override;
void update(Command) override;
void update(Command /*command*/) override;
void block();
[[nodiscard]] Rank getRank() const;

2
src/libdramsys/DRAMSys/controller/Command.h
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@@ -84,7 +84,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 26
DECLARE_EXTENDED_PHASE(END_SREF); // 27
#ifdef DRAMPOWER
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase /*phase*/ /*phase*/);
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase);

2
src/libdramsys/DRAMSys/controller/Controller.cpp
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@@ -440,7 +440,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase&
return TLM_ACCEPTED;
}
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&)
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& /*trans*/,tlm_phase& /*phase*/, sc_time& /*delay*/)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!");
return TLM_ACCEPTED;

4
src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp
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@@ -65,8 +65,8 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans,
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&,
tlm_phase&, sc_time&)
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload& /*trans*/,
tlm_phase& /*phase*/, sc_time& /*delay*/)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called");
return TLM_ACCEPTED;

2
src/libdramsys/DRAMSys/controller/ManagerIF.h
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@@ -45,7 +45,7 @@ class ManagerIF
public:
virtual void evaluate() = 0;
virtual CommandTuple::Type getNextCommand() = 0;
virtual void update(Command) = 0;
virtual void update(Command /*command*/) = 0;
virtual ~ManagerIF() = default;
};

2
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h
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@@ -44,7 +44,7 @@ class CmdMuxIF
{
public:
virtual ~CmdMuxIF() = default;
virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0;
virtual CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) = 0;
};
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h
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@@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF
{
public:
explicit CmdMuxOldest(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override;
private:
const MemSpec& memSpec;
@@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF
{
public:
explicit CmdMuxOldestRasCas(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override;
private:
const MemSpec& memSpec;

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h
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@@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF
{
public:
explicit CmdMuxStrict(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override;
private:
uint64_t nextPayloadID = 1;
@@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF
{
public:
explicit CmdMuxStrictRasCas(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override;
private:
uint64_t nextPayloadID = 1;

2
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -50,7 +50,7 @@ public:
void triggerInterruption() override {}
CommandTuple::Type getNextCommand() override;
void update(Command) override {}
void update(Command /*command*/) override {}
void evaluate() override {}
};

2
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -57,7 +57,7 @@ public:
void triggerInterruption() override;
CommandTuple::Type getNextCommand() override;
void update(Command) override;
void update(Command /*command*/) override;
void evaluate() override;
private:

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h
View File

@@ -58,7 +58,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command /*command*/) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h
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@@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF
public:
CommandTuple::Type getNextCommand() override;
void evaluate() override {}
void update(Command) override {}
void update(Command /*command*/) override {}
sc_core::sc_time getTimeForNextTrigger() override;
private:
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h
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@@ -60,7 +60,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command /*command*/) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h
View File

@@ -60,7 +60,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command /*command*/) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h
View File

@@ -59,7 +59,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command /*command*/) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h
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@@ -48,7 +48,7 @@ namespace DRAMSys
class RespQueueFifo final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;

2
src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h
View File

@@ -44,7 +44,7 @@ namespace DRAMSys
class RespQueueIF
{
public:
virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0;
virtual void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) = 0;
virtual tlm::tlm_generic_payload* nextPayload() = 0;
[[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() = default;

2
src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h
View File

@@ -47,7 +47,7 @@ namespace DRAMSys
class RespQueueReorder final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h
View File

@@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF
public:
explicit SchedulerFifo(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& /*payload*/) override;
void removeRequest(tlm::tlm_generic_payload& /*payload*/) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF
public:
explicit SchedulerFrFcfs(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& /*payload*/) override;
void removeRequest(tlm::tlm_generic_payload& /*payload*/) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF
public:
explicit SchedulerFrFcfsGrp(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& /*payload*/) override;
void removeRequest(tlm::tlm_generic_payload& /*payload*/) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h
View File

@@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF
public:
explicit SchedulerGrpFrFcfs(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& /*payload*/) override;
void removeRequest(tlm::tlm_generic_payload& /*payload*/) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h
View File

@@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF
public:
explicit SchedulerGrpFrFcfsWm(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& /*payload*/) override;
void removeRequest(tlm::tlm_generic_payload& /*payload*/) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h
View File

@@ -50,11 +50,11 @@ class SchedulerIF
public:
virtual ~SchedulerIF() = default;
[[nodiscard]] virtual bool hasBufferSpace() const = 0;
virtual void storeRequest(tlm::tlm_generic_payload&) = 0;
virtual void removeRequest(tlm::tlm_generic_payload&) = 0;
[[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const = 0;
[[nodiscard]] virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0;
[[nodiscard]] virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0;
virtual void storeRequest(tlm::tlm_generic_payload& /*payload*/) = 0;
virtual void removeRequest(tlm::tlm_generic_payload& /*payload*/) = 0;
[[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const = 0;
[[nodiscard]] virtual bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const = 0;
[[nodiscard]] virtual bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const = 0;
[[nodiscard]] virtual const std::vector<unsigned>& getBufferDepth() const = 0;
};

4
src/libdramsys/DRAMSys/simulation/Arbiter.cpp
View File

@@ -156,7 +156,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans,
return TLM_ACCEPTED;
}
tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload,
tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload,
tlm_phase& phase, sc_time& bwDelay)
{
PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " +
@@ -165,7 +165,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload,
return TLM_ACCEPTED;
}
void Arbiter::b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
{
trans.set_address(trans.get_address() - addressOffset);

4
src/libdramsys/DRAMSys/simulation/Arbiter.h
View File

@@ -87,9 +87,9 @@ protected:
tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_core::sc_time& fwDelay);
tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload,
tlm::tlm_sync_enum nb_transport_bw(int /*id*/, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_core::sc_time &bwDelay);
void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
void b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans);
const sc_core::sc_time tCK;