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Merge branch 'develop' into work/partial_writes

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This commit is contained in:
Derek Christ
2023-08-23 09:31:42 +02:00
parent 0d67a1fc2b 5250adea3c
commit a539e3c011
129 changed files with 1127 additions and 994 deletions
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11
.clang-format Executable file
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@@ -0,0 +1,11 @@
AccessModifierOffset: '-4'
AllowShortFunctionsOnASingleLine: InlineOnly
AllowShortIfStatementsOnASingleLine: Never
BinPackArguments: 'false'
BinPackParameters: 'false'
BreakBeforeBraces: Allman
BreakConstructorInitializers: AfterColon
ColumnLimit: '100'
ConstructorInitializerAllOnOneLineOrOnePerLine: 'true'
IndentWidth: '4'
PointerAlignment: Left

18
.clang-tidy Normal file
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@@ -0,0 +1,18 @@
Checks: >
clang-diagnostic-*,
clang-analyzer-*,
modernize-*,
bugprone-*,
concurrency-*,
cppcoreguidelines-*,
performance-*,
portability-*,
readability-*,
-modernize-use-trailing-return-type,
-readability-braces-around-statements,
-readability-identifier-length,
-readability-function-cognitive-complexity
WarningsAsErrors: ''
HeaderFilterRegex: ''
AnalyzeTemporaryDtors: false
FormatStyle: file

3
CMakePresets.json
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@@ -69,7 +69,8 @@
"std"
],
"cacheVariables": {
"CMAKE_BUILD_TYPE": "Debug"
"CMAKE_BUILD_TYPE": "Debug",
"CMAKE_CXX_FLAGS": "-Wall -Wextra -Wpedantic"
}
}
]

13
extensions/apps/traceAnalyzer/.clang-format
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@@ -1,13 +0,0 @@
---
BasedOnStyle: LLVM
AccessModifierOffset: '-4'
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: Never
AllowShortLoopsOnASingleLine: 'false'
AlwaysBreakTemplateDeclarations: 'true'
BreakBeforeBraces: Allman
ColumnLimit: '120'
IndentWidth: '4'
PointerAlignment: Right
...

16
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -59,30 +59,30 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")),
tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")),
//tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
//tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")),
tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
//tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
//tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
//tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
//tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
//tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
@@ -104,10 +104,10 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")),
tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
tBURST16(tCK * 16 / dataRate),
tBURST32(tCK * 32 / dataRate),
bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B))
bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset"))
{
commandLengthInCycles[Command::ACT] = 2;

3
src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp
View File

@@ -124,9 +124,8 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector
if (file.is_open()) {
json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY);
return simulation.get<DRAMSys::Config::Configuration>();
} else {
throw std::runtime_error("Failed to open file " + std::string(path));
}
throw std::runtime_error("Failed to open file " + std::string(path));
}
} // namespace DRAMSys::Config

22
src/configuration/DRAMSys/config/TraceSetup.h
View File

@@ -70,7 +70,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid
struct TracePlayer
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -81,10 +81,10 @@ NLOHMANN_JSONIFY_ALL_THINGS(
struct TrafficGeneratorActiveState
{
unsigned int id;
unsigned int id{};
uint64_t numRequests;
double rwRatio;
uint64_t numRequests{};
double rwRatio{};
AddressDistribution addressDistribution;
std::optional<uint64_t> addressIncrement;
std::optional<uint64_t> minAddress;
@@ -120,7 +120,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probabili
struct TrafficGenerator
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -130,8 +130,8 @@ struct TrafficGenerator
std::optional<unsigned> dataLength;
std::optional<unsigned> dataAlignment;
uint64_t numRequests;
double rwRatio;
uint64_t numRequests{};
double rwRatio{};
AddressDistribution addressDistribution;
std::optional<uint64_t> addressIncrement;
std::optional<uint64_t> minAddress;
@@ -156,7 +156,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator,
struct TrafficGeneratorStateMachine
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
@@ -183,13 +183,13 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine,
struct RowHammer
{
uint64_t clkMhz;
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
uint64_t numRequests;
uint64_t rowIncrement;
uint64_t numRequests{};
uint64_t rowIncrement{};
};
NLOHMANN_JSONIFY_ALL_THINGS(

5
src/libdramsys/DRAMSys/common/DebugManager.cpp
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@@ -74,10 +74,7 @@ void DebugManager::openDebugFile(const std::string &filename)
debugFile.open(filename);
}
DebugManager::DebugManager()
: debugEnabled(false), writeToConsole(false), writeToFile(false)
{
}
DebugManager::DebugManager() = default;
DebugManager::~DebugManager()
{

9
src/libdramsys/DRAMSys/common/DebugManager.h
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@@ -64,8 +64,9 @@ private:
public:
DebugManager(const DebugManager&) = delete;
DebugManager& operator=(const DebugManager&) = delete;
DebugManager(DebugManager&&) = delete;
DebugManager& operator=(DebugManager&&) = delete;
public:
void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile);
void printDebugMessage(const std::string &sender, const std::string &message);
@@ -73,9 +74,9 @@ public:
void openDebugFile(const std::string &filename);
private:
bool debugEnabled;
bool writeToConsole;
bool writeToFile;
bool debugEnabled = false;
bool writeToConsole = false;
bool writeToFile = false;
std::ofstream debugFile;
};

23
src/libdramsys/DRAMSys/common/TlmRecorder.cpp
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@@ -52,18 +52,21 @@ using namespace tlm;
namespace DRAMSys
{
TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) :
name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
TlmRecorder::TlmRecorder(const std::string &name,
const Configuration &config,
const std::string &dbName) :
name(name),
config(config),
memSpec(*config.memSpec),
currentDataBuffer(&recordingDataBuffer.at(0)),
storageDataBuffer(&recordingDataBuffer.at(1)),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
{
currentDataBuffer = &recordingDataBuffer[0];
storageDataBuffer = &recordingDataBuffer[1];
currentDataBuffer->reserve(transactionCommitRate);
storageDataBuffer->reserve(transactionCommitRate);
openDB(dbName);
char *sErrMsg;
char *sErrMsg = nullptr;
sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg);
sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg);
sqlite3_exec(db, "PRAGMA main.locking_mode=EXCLUSIVE", nullptr, nullptr, &sErrMsg);
@@ -81,7 +84,7 @@ TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, c
void TlmRecorder::finalize()
{
if (db)
if (db != nullptr)
closeConnection();
sqlite3_finalize(insertTransactionStatement);
sqlite3_finalize(insertRangeStatement);
@@ -149,7 +152,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase
}
else if (isFixedCommandPhase(phase))
{
tlm_generic_payload* keyTrans;
tlm_generic_payload* keyTrans = nullptr;
if (ChildExtension::isChildTrans(trans))
{
keyTrans = &ChildExtension::getParentTrans(trans);
@@ -213,7 +216,7 @@ void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans)
{
totalNumTransactions++;
char commandChar;
char commandChar = 0;
tlm_command command = trans.get_command();
if (command == TLM_READ_COMMAND)
commandChar = 'R';

13
src/libdramsys/DRAMSys/common/TlmRecorder.h
View File

@@ -63,8 +63,11 @@ class TlmRecorder
{
public:
TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName);
TlmRecorder(const TlmRecorder&) = delete;
TlmRecorder(TlmRecorder&&) = default;
TlmRecorder(const TlmRecorder &) = delete;
TlmRecorder(TlmRecorder &&) = default;
TlmRecorder &operator=(const TlmRecorder &) = delete;
TlmRecorder &operator=(TlmRecorder &&) = delete;
~TlmRecorder() = default;
void recordMcConfig(std::string _mcconfig)
{
@@ -89,12 +92,12 @@ public:
void finalize();
private:
std::string name;
const Configuration& config;
const MemSpec& memSpec;
struct Transaction
{
Transaction(const Transaction& other) = default;
Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd,
const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) :
id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration),
@@ -131,8 +134,6 @@ private:
std::vector<Phase> recordedPhases;
};
std::string name;
std::string mcconfig, memspec, traces;
void prepareSqlStatements();
@@ -162,7 +163,7 @@ private:
std::unordered_map<tlm::tlm_generic_payload*, Transaction> currentTransactionsInSystem;
uint64_t totalNumTransactions;
uint64_t totalNumTransactions = 0;
sc_core::sc_time simulationTimeCoveredByRecording;
sqlite3 *db = nullptr;

11
src/libdramsys/DRAMSys/common/dramExtensions.cpp
View File

@@ -310,10 +310,7 @@ void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm
bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans)
{
if (trans.get_extension<ChildExtension>() != nullptr)
return true;
else
return false;
return trans.get_extension<ChildExtension>() != nullptr;
}
tlm_extension_base* ParentExtension::clone() const
@@ -358,10 +355,8 @@ bool ParentExtension::notifyChildTransCompletion()
childTranses.clear();
return true;
}
else
{
return false;
}
return false;
}
bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans)

37
src/libdramsys/DRAMSys/common/dramExtensions.h
View File

@@ -87,13 +87,13 @@ public:
static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID,
const sc_core::sc_time& timeOfGeneration);
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
Thread getThread() const;
Channel getChannel() const;
uint64_t getThreadPayloadID() const;
sc_core::sc_time getTimeOfGeneration() const;
[[nodiscard]] Thread getThread() const;
[[nodiscard]] Channel getChannel() const;
[[nodiscard]] uint64_t getThreadPayloadID() const;
[[nodiscard]] sc_core::sc_time getTimeOfGeneration() const;
static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans);
static Thread getThread(const tlm::tlm_generic_payload& trans);
@@ -120,16 +120,16 @@ public:
//static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans);
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
uint64_t getChannelPayloadID() const;
Rank getRank() const;
BankGroup getBankGroup() const;
Bank getBank() const;
Row getRow() const;
Column getColumn() const;
unsigned getBurstLength() const;
[[nodiscard]] uint64_t getChannelPayloadID() const;
[[nodiscard]] Rank getRank() const;
[[nodiscard]] BankGroup getBankGroup() const;
[[nodiscard]] Bank getBank() const;
[[nodiscard]] Row getRow() const;
[[nodiscard]] Column getColumn() const;
[[nodiscard]] unsigned getBurstLength() const;
static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans);
static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans);
@@ -161,7 +161,7 @@ private:
public:
//ChildExtension() = delete;
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
tlm::tlm_generic_payload& getParentTrans();
static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans);
@@ -180,7 +180,7 @@ private:
public:
ParentExtension() = delete;
tlm_extension_base* clone() const override;
[[nodiscard]] tlm_extension_base* clone() const override;
void copy_from(const tlm_extension_base& ext) override;
static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector<tlm::tlm_generic_payload*> childTranses);
const std::vector<tlm::tlm_generic_payload*>& getChildTranses();
@@ -191,15 +191,12 @@ public:
class EccExtension : public tlm::tlm_extension<EccExtension>
{
public:
tlm_extension_base* clone() const override
[[nodiscard]] tlm_extension_base* clone() const override
{
return new EccExtension;
}
void copy_from(tlm_extension_base const &ext) override
{
auto const &cpyFrom = static_cast<EccExtension const &>(ext);
}
void copy_from([[maybe_unused]] tlm_extension_base const & ext) override {}
};
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/common/utils.cpp
View File

@@ -60,10 +60,10 @@ bool TimeInterval::intersects(const TimeInterval &other) const
sc_time TimeInterval::getLength() const
{
if (end > start)
return end - start;
else
if (start > end)
return start - end;
return end - start;
}
std::string getPhaseName(const tlm_phase &phase)

8
src/libdramsys/DRAMSys/common/utils.h
View File

@@ -56,12 +56,12 @@ public:
TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {}
TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {}
sc_core::sc_time getLength() const;
bool timeIsInInterval(const sc_core::sc_time &time) const;
bool intersects(const TimeInterval &other) const;
[[nodiscard]] sc_core::sc_time getLength() const;
[[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const;
[[nodiscard]] bool intersects(const TimeInterval &other) const;
};
constexpr const char headline[] =
constexpr const std::string_view headline =
"===========================================================================";
std::string getPhaseName(const tlm::tlm_phase &phase);

24
src/libdramsys/DRAMSys/configuration/Configuration.cpp
View File

@@ -71,21 +71,25 @@ enum sc_time_unit string2TimeUnit(const std::string &s)
{
if (s == "s")
return SC_SEC;
else if (s == "ms")
if (s == "ms")
return SC_MS;
else if (s == "us")
if (s == "us")
return SC_US;
else if (s == "ns")
if (s == "ns")
return SC_NS;
else if (s == "ps")
if (s == "ps")
return SC_PS;
else if (s == "fs")
if (s == "fs")
return SC_FS;
else {
SC_REPORT_FATAL("Configuration",
("Could not convert to enum sc_time_unit: " + s).c_str());
throw;
}
SC_REPORT_FATAL("Configuration",
("Could not convert to enum sc_time_unit: " + s).c_str());
throw;
}
void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig)

5
src/libdramsys/DRAMSys/configuration/Configuration.h
View File

@@ -54,11 +54,6 @@ namespace DRAMSys
class Configuration
{
public:
Configuration() = default;
Configuration(const Configuration&) = delete;
Configuration& operator=(const Configuration &) = delete;
public:
// MCConfig:
enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open;

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
View File

@@ -75,8 +75,8 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec,
tCK(sc_time(1.0 / fCKMHz, SC_US)),
memoryId(memSpec.memoryId),
memoryType(memoryType),
burstDuration(tCK* (static_cast<double>(defaultBurstLength) / dataRate)),
memorySizeBytes(0)
burstDuration(tCK* (static_cast<double>(defaultBurstLength) / dataRate))
{
commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
}

42
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
View File

@@ -54,6 +54,10 @@ namespace DRAMSys
class MemSpec
{
public:
MemSpec &operator=(const MemSpec &) = delete;
MemSpec &operator=(MemSpec &&) = delete;
virtual ~MemSpec() = default;
const unsigned numberOfChannels;
const unsigned pseudoChannelsPerChannel;
const unsigned ranksPerChannel;
@@ -84,29 +88,26 @@ public:
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, HBM3, STTMRAM
} memoryType;
virtual ~MemSpec() = default;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalSB() const;
virtual sc_core::sc_time getRefreshIntervalAB() const;
virtual sc_core::sc_time getRefreshIntervalPB() const;
virtual sc_core::sc_time getRefreshIntervalP2B() const;
virtual sc_core::sc_time getRefreshIntervalSB() const;
[[nodiscard]] virtual unsigned getPer2BankOffset() const;
virtual unsigned getPer2BankOffset() const;
[[nodiscard]] virtual unsigned getRAAIMT() const;
[[nodiscard]] virtual unsigned getRAAMMT() const;
[[nodiscard]] virtual unsigned getRAADEC() const;
virtual unsigned getRAAIMT() const;
virtual unsigned getRAAMMT() const;
virtual unsigned getRAADEC() const;
[[nodiscard]] virtual bool hasRasAndCasBus() const;
virtual bool hasRasAndCasBus() const;
[[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
sc_core::sc_time getCommandLength(Command) const;
double getCommandLengthInCycles(Command) const;
uint64_t getSimMemSizeInBytes() const;
[[nodiscard]] sc_core::sc_time getCommandLength(Command command) const;
[[nodiscard]] double getCommandLengthInCycles(Command command) const;
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
protected:
MemSpec(const DRAMSys::Config::MemSpec& memSpec,
@@ -117,10 +118,13 @@ protected:
unsigned banksPerChannel, unsigned bankGroupsPerChannel,
unsigned devicesPerRank);
MemSpec(const MemSpec &) = default;
MemSpec(MemSpec &&) = default;
// Command lengths in cycles on bus, usually one clock cycle
std::vector<double> commandLengthInCycles;
sc_core::sc_time burstDuration;
uint64_t memorySizeBytes;
uint64_t memorySizeBytes = 0;
};
} // namespace DRAMSys

52
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -61,7 +61,6 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec)
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
@@ -71,16 +70,17 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec)
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
@@ -127,41 +127,45 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h
View File

@@ -93,10 +93,10 @@ public:
const double iDD3P0;
const double iDD3P1;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

43
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -146,41 +146,44 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
View File

@@ -100,10 +100,10 @@ public:
const double iDD62;
const double vDD2;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

48
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -130,44 +130,48 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD;
else
return tRCDWR;
return tRCDWR;
}
else if (command == Command::RD)
if (command == Command::RD)
return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else if (command == Command::REFPB)
if (command == Command::REFPB)
return tRFCPB;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h
View File

@@ -90,11 +90,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

48
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -130,44 +130,48 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD;
else
return tRCDWR;
return tRCDWR;
}
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else if (command == Command::REFPB)
if (command == Command::REFPB)
return tRFCPB;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -90,11 +90,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

52
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -60,7 +60,6 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups")
* memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
@@ -96,7 +95,8 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec)
tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")),
tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")),
tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
@@ -143,44 +143,48 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + tCK;
else
return tRCDWR + tCK;
return tRCDWR + tCK;
}
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFCab;
else if (command == Command::REFPB || command == Command::REFP2B)
if (command == Command::REFPB || command == Command::REFP2B)
return tRFCpb;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

12
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h
View File

@@ -91,13 +91,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalP2B() const override;
unsigned getPer2BankOffset() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
[[nodiscard]] unsigned getPer2BankOffset() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
private:
unsigned per2BankOffset;

48
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -131,44 +131,48 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + tCK;
else
return tRCDWR + tCK;
return tRCDWR + tCK;
}
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else if (command == Command::REFPB)
if (command == Command::REFPB)
return tRFCSB;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

10
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h
View File

@@ -85,13 +85,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
bool hasRasAndCasBus() const override;
[[nodiscard]] bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

53
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -62,12 +62,12 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec)
tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")),
tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")),
tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")),
tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")),
tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
@@ -135,45 +135,50 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const
return tREFIpb;
}
sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB)
return tRPpb + tCK;
else if (command == Command::PREAB)
if (command == Command::PREAB)
return tRPab + tCK;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD + 3 * tCK;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tDQSCK + burstDuration + 3 * tCK;
else if (command == Command::RDA)
if (command == Command::RDA)
return burstDuration + tRTP - 5 * tCK + tRPpb;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + 4 * tCK + burstDuration + tWR + tRPpb;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFCab + tCK;
else if (command == Command::REFPB)
if (command == Command::REFPB)
return tRFCpb + tCK;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK};
else
{
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -87,11 +87,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

46
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -61,7 +61,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
@@ -71,14 +70,15 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")),
tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")),
tAL (tCK * memSpec.memtimingspec.entries.at("AL")),
tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS"))
@@ -104,39 +104,41 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tWR + tRP;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -78,8 +78,8 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

51
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -60,8 +60,6 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tAC (tCK * memSpec.memtimingspec.entries.at("AC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
@@ -70,11 +68,13 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec)
tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")),
tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")),
tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")),
tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tAC (tCK * memSpec.memtimingspec.entries.at("AC")),
tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")),
tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")),
tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")),
@@ -133,41 +133,44 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tAC + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return burstDuration + tRP;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration - tCK + tWR + tRP;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFC;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tAC, tRL + tAC + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h
View File

@@ -98,10 +98,10 @@ public:
const double iDD62;
const double vDD2;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

49
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -117,45 +117,50 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const
sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::PREPB)
return tRPpb;
else if (command == Command::PREAB)
if (command == Command::PREAB)
return tRPab;
else if (command == Command::ACT)
if (command == Command::ACT)
return tRCD;
else if (command == Command::RD)
if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
else if (command == Command::RDA)
if (command == Command::RDA)
return burstDuration - 2 * tCK + tRTP + tRPpb;
else if (command == Command::WR || command == Command::MWR)
if (command == Command::WR || command == Command::MWR)
return tWL + tDQSS + burstDuration;
else if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA || command == Command::MWRA)
return tWL + burstDuration + tCK + tWR + tRPpb;
else if (command == Command::REFAB)
if (command == Command::REFAB)
return tRFCab;
else if (command == Command::REFPB)
if (command == Command::REFPB)
return tRFCpb;
else
{
SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime",
"command not known or command doesn't have a fixed execution time");
throw;
}
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
return {tWL + tDQSS, tWL + tDQSS + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return {};
}
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
throw;
}
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h
View File

@@ -79,11 +79,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

229
src/libdramsys/DRAMSys/controller/BankMachine.cpp
View File

@@ -44,12 +44,15 @@ using namespace tlm;
namespace DRAMSys
{
BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank)
: scheduler(scheduler), memSpec(*config.memSpec), bank(bank),
BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) :
memSpec(*config.memSpec),
scheduler(scheduler),
bank(bank),
bankgroup(BankGroup(static_cast<std::size_t>(bank) / memSpec.banksPerGroup)),
rank(Rank(static_cast<std::size_t>(bank) / memSpec.banksPerRank)),
refreshManagement(config.refreshManagement)
{}
{
}
CommandTuple::Type BankMachine::getNextCommand()
{
@@ -172,41 +175,37 @@ void BankMachineOpen::evaluate()
if (!(sleeping || blocked))
{
tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
tlm_generic_payload *newPayload = scheduler.getNextRequest(*this);
if (newPayload == nullptr)
{
return;
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
currentPayload = newPayload;
}
currentPayload = newPayload;
}
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
else // row miss
nextCommand = Command::PREPB;
}
else // row miss
nextCommand = Command::PREPB;
}
}
}
@@ -220,35 +219,31 @@ void BankMachineClosed::evaluate()
if (!(sleeping || blocked))
{
tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
tlm_generic_payload *newPayload = scheduler.getNextRequest(*this);
if (newPayload == nullptr)
{
return;
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
currentPayload = newPayload;
}
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
currentPayload = newPayload;
}
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}
@@ -263,55 +258,51 @@ void BankMachineOpenAdaptive::evaluate()
if (!(sleeping || blocked))
{
tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
tlm_generic_payload *newPayload = scheduler.getNextRequest(*this);
if (newPayload == nullptr)
{
return;
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
currentPayload = newPayload;
}
currentPayload = newPayload;
}
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) &&
!scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
{
if (scheduler.hasFurtherRequest(bank, currentPayload->get_command())
&& !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
else
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else // row miss
nextCommand = Command::PREPB;
}
else // row miss
nextCommand = Command::PREPB;
}
}
}
@@ -326,54 +317,50 @@ void BankMachineClosedAdaptive::evaluate()
if (!(sleeping || blocked))
{
tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
tlm_generic_payload *newPayload = scheduler.getNextRequest(*this);
if (newPayload == nullptr)
{
return;
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
assert(!keepTrans || currentPayload != nullptr);
if (keepTrans)
{
if (ControllerExtension::getRow(*newPayload) == openRow)
currentPayload = newPayload;
}
else
{
currentPayload = newPayload;
}
currentPayload = newPayload;
}
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
if (state == State::Precharged) // bank precharged
nextCommand = Command::ACT;
else if (state == State::Activated)
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
{
if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit
if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
{
if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RD;
else
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else
{
assert(currentPayload->is_read() || currentPayload->is_write());
if (currentPayload->is_read())
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
else // row miss, can happen when RD/WR mode is switched
nextCommand = Command::PREPB;
}
else // row miss, can happen when RD/WR mode is switched
nextCommand = Command::PREPB;
}
}
}

2
src/libdramsys/DRAMSys/controller/BankMachine.h
View File

@@ -53,7 +53,7 @@ class BankMachine : public ManagerIF
{
public:
CommandTuple::Type getNextCommand() override;
void update(Command) override;
void update(Command command) override;
void block();
[[nodiscard]] Rank getRank() const;

2
src/libdramsys/DRAMSys/controller/Command.h
View File

@@ -86,7 +86,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 28
DECLARE_EXTENDED_PHASE(END_SREF); // 29
#ifdef DRAMPOWER
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase);
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase);

30
src/libdramsys/DRAMSys/controller/Controller.cpp
View File

@@ -80,10 +80,10 @@ namespace DRAMSys
{
Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) :
ControllerIF(name, config), addressDecoder(addressDecoder),
thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw),
phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw),
blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay),
ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw),
thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw),
phyDelayBw(config.phyDelayBw), blockingReadDelay(config.blockingReadDelay),
blockingWriteDelay(config.blockingWriteDelay), addressDecoder(addressDecoder),
minBytesPerBurst(config.memSpec->defaultBytesPerBurst),
maxBytesPerBurst(config.memSpec->maxBytesPerBurst)
{
@@ -207,8 +207,8 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
{
for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++)
{
powerDownManagers.push_back(std::make_unique<PowerDownManagerStaggered>(bankMachinesOnRank[Rank(rankID)],
Rank(rankID), *checker));
powerDownManagers.push_back(std::make_unique<PowerDownManagerStaggered>(
bankMachinesOnRank[Rank(rankID)], Rank(rankID)));
}
}
@@ -293,7 +293,7 @@ void Controller::controllerMethod()
readyCommands.emplace_back(commandTuple);
// (4.3) Check for bank commands (PREPB, ACT, RD/RDA or WR/WRA)
for (auto it : bankMachinesOnRank[rank])
for (auto* it : bankMachinesOnRank[rank])
{
commandTuple = it->getNextCommand();
if (std::get<CommandTuple::Command>(commandTuple) != Command::NOP)
@@ -322,7 +322,7 @@ void Controller::controllerMethod()
if (command.isRankCommand())
{
for (auto it : bankMachinesOnRank[rank])
for (auto* it : bankMachinesOnRank[rank])
it->update(command);
}
else if (command.isGroupCommand())
@@ -442,7 +442,9 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase&
return TLM_ACCEPTED;
}
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&)
tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans,
[[maybe_unused]] tlm_phase &phase,
[[maybe_unused]] sc_time &delay)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!");
return TLM_ACCEPTED;
@@ -623,12 +625,10 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate()
{
return *new tlm_generic_payload(this);
}
else
{
tlm_generic_payload* result = freePayloads.top();
freePayloads.pop();
return *result;
}
tlm_generic_payload *result = freePayloads.top();
freePayloads.pop();
return *result;
}
void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans)

6
src/libdramsys/DRAMSys/controller/Controller.h
View File

@@ -116,7 +116,13 @@ private:
class MemoryManager : public tlm::tlm_mm_interface
{
public:
MemoryManager() = default;
MemoryManager(const MemoryManager &) = delete;
MemoryManager(MemoryManager &&) = delete;
MemoryManager &operator=(const MemoryManager &) = delete;
MemoryManager &operator=(MemoryManager &&) = delete;
~MemoryManager() override;
tlm::tlm_generic_payload& allocate();
void free(tlm::tlm_generic_payload* trans) override;

9
src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp
View File

@@ -45,8 +45,8 @@ namespace DRAMSys
ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config,
const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder)
: Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder),
activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing),
windowSizeTime(config.windowSize * memSpec.tCK)
windowSizeTime(config.windowSize * memSpec.tCK), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate),
enableWindowing(config.enableWindowing)
{
if (enableWindowing)
{
@@ -65,8 +65,9 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans,
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&,
tlm_phase&, sc_time&)
tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans,
[[maybe_unused]] tlm_phase &phase,
[[maybe_unused]] sc_time &delay)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called");
return TLM_ACCEPTED;

4
src/libdramsys/DRAMSys/controller/ControllerRecordable.h
View File

@@ -49,7 +49,6 @@ class ControllerRecordable final : public Controller
public:
ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config,
const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder);
~ControllerRecordable() override = default;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
@@ -57,7 +56,8 @@ protected:
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override;
void sendToFrontend(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
void controllerMethod() override;

12
src/libdramsys/DRAMSys/controller/ManagerIF.h
View File

@@ -42,11 +42,19 @@ namespace DRAMSys
class ManagerIF
{
protected:
ManagerIF(const ManagerIF &) = default;
ManagerIF(ManagerIF &&) = default;
ManagerIF &operator=(const ManagerIF &) = default;
ManagerIF &operator=(ManagerIF &&) = default;
public:
ManagerIF() = default;
virtual ~ManagerIF() = default;
virtual void evaluate() = 0;
virtual CommandTuple::Type getNextCommand() = 0;
virtual void update(Command) = 0;
virtual ~ManagerIF() = default;
virtual void update(Command command) = 0;
};
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerDDR3::CheckerDDR3(const Configuration& config)
CheckerDDR3::CheckerDDR3(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecDDR3*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecDDR3 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h
View File

@@ -49,7 +49,7 @@ class CheckerDDR3 final : public CheckerIF
{
public:
explicit CheckerDDR3(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerDDR4::CheckerDDR4(const Configuration& config)
CheckerDDR4::CheckerDDR4(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecDDR4*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecDDR4 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h
View File

@@ -51,7 +51,7 @@ class CheckerDDR4 final : public CheckerIF
{
public:
explicit CheckerDDR4(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR5::CheckerGDDR5(const Configuration& config)
CheckerGDDR5::CheckerGDDR5(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR5*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR5 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h
View File

@@ -49,7 +49,7 @@ class CheckerGDDR5 final : public CheckerIF
{
public:
explicit CheckerGDDR5(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR5X::CheckerGDDR5X(const Configuration& config)
CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR5X*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR5X *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h
View File

@@ -49,7 +49,7 @@ class CheckerGDDR5X final : public CheckerIF
{
public:
explicit CheckerGDDR5X(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerGDDR6::CheckerGDDR6(const Configuration& config)
CheckerGDDR6::CheckerGDDR6(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecGDDR6*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecGDDR6 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h
View File

@@ -49,7 +49,7 @@ class CheckerGDDR6 final : public CheckerIF
{
public:
explicit CheckerGDDR6(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerHBM2::CheckerHBM2(const Configuration& config)
CheckerHBM2::CheckerHBM2(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecHBM2*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecHBM2 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h
View File

@@ -49,7 +49,7 @@ class CheckerHBM2 final : public CheckerIF
{
public:
explicit CheckerHBM2(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

9
src/libdramsys/DRAMSys/controller/checker/CheckerIF.h
View File

@@ -44,10 +44,17 @@ namespace DRAMSys
class CheckerIF
{
protected:
CheckerIF(const CheckerIF &) = default;
CheckerIF(CheckerIF &&) = default;
CheckerIF &operator=(const CheckerIF &) = default;
CheckerIF &operator=(CheckerIF &&) = default;
public:
CheckerIF() = default;
virtual ~CheckerIF() = default;
virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0;
};

4
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerLPDDR4::CheckerLPDDR4(const Configuration& config)
CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecLPDDR4*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecLPDDR4 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h
View File

@@ -49,7 +49,7 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
explicit CheckerLPDDR4(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config)
CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecSTTMRAM*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecSTTMRAM *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h
View File

@@ -49,7 +49,7 @@ class CheckerSTTMRAM final : public CheckerIF
{
public:
explicit CheckerSTTMRAM(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerWideIO::CheckerWideIO(const Configuration& config)
CheckerWideIO::CheckerWideIO(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecWideIO*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecWideIO *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h
View File

@@ -49,7 +49,7 @@ class CheckerWideIO final : public CheckerIF
{
public:
explicit CheckerWideIO(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

4
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp
View File

@@ -44,9 +44,9 @@ using namespace tlm;
namespace DRAMSys
{
CheckerWideIO2::CheckerWideIO2(const Configuration& config)
CheckerWideIO2::CheckerWideIO2(const Configuration& config) :
memSpec(dynamic_cast<const MemSpecWideIO2*>(config.memSpec.get()))
{
memSpec = dynamic_cast<const MemSpecWideIO2 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen");

2
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h
View File

@@ -49,7 +49,7 @@ class CheckerWideIO2 final : public CheckerIF
{
public:
explicit CheckerWideIO2(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

10
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h
View File

@@ -42,9 +42,17 @@ namespace DRAMSys
class CmdMuxIF
{
protected:
CmdMuxIF(const CmdMuxIF &) = default;
CmdMuxIF(CmdMuxIF &&) = default;
CmdMuxIF &operator=(const CmdMuxIF &) = default;
CmdMuxIF &operator=(CmdMuxIF &&) = default;
public:
CmdMuxIF() = default;
virtual ~CmdMuxIF() = default;
virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0;
virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0;
};
} // namespace DRAMSys

10
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand
{
auto result = readyCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -73,8 +73,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand
if (result != readyCommands.cend() &&
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
return *result;
else
return {Command::NOP, nullptr, scMaxTime};
return {Command::NOP, nullptr, scMaxTime};
}
@@ -103,7 +102,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
auto resultCas = readyCasCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -179,8 +178,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
if (result != readyCommands.cend() &&
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
return *result;
else
return {Command::NOP, nullptr, scMaxTime};
return {Command::NOP, nullptr, scMaxTime};
}
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h
View File

@@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF
{
public:
explicit CmdMuxOldest(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override;
private:
const MemSpec& memSpec;
@@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF
{
public:
explicit CmdMuxOldestRasCas(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override;
private:
const MemSpec& memSpec;

10
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
{
auto result = readyCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -83,8 +83,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
nextPayloadID++;
return *result;
}
else
return {Command::NOP, nullptr, scMaxTime};
return {Command::NOP, nullptr, scMaxTime};
}
@@ -113,7 +112,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
auto resultCas = readyCasCommands.cend();
uint64_t lastPayloadID = UINT64_MAX;
uint64_t newPayloadID;
uint64_t newPayloadID = 0;
sc_time lastTimestamp = scMaxTime;
sc_time newTimestamp;
@@ -181,8 +180,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
if (std::get<CommandTuple::Command>(*result).isCasCommand())
nextPayloadID++;
return *result;
}
else
}
return {Command::NOP, nullptr, scMaxTime};
}

4
src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h
View File

@@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF
{
public:
explicit CmdMuxStrict(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override;
private:
uint64_t nextPayloadID = 1;
@@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF
{
public:
explicit CmdMuxStrictRasCas(const Configuration& config);
CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override;
private:
uint64_t nextPayloadID = 1;

2
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -50,7 +50,7 @@ public:
void triggerInterruption() override {}
CommandTuple::Type getNextCommand() override;
void update(Command) override {}
void update([[maybe_unused]] Command command) override {}
void evaluate() override {}
};

8
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -42,9 +42,9 @@ using namespace tlm;
namespace DRAMSys
{
PowerDownManagerStaggered::PowerDownManagerStaggered(ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
Rank rank, CheckerIF& checker)
: bankMachinesOnRank(bankMachinesOnRank)
PowerDownManagerStaggered::PowerDownManagerStaggered(
ControllerVector<Bank, BankMachine*>& bankMachinesOnRank, Rank rank) :
bankMachinesOnRank(bankMachinesOnRank)
{
setUpDummy(powerDownPayload, UINT64_MAX - 1, rank);
}
@@ -98,7 +98,7 @@ void PowerDownManagerStaggered::evaluate()
else if (entryTriggered)
{
nextCommand = Command::PDEP;
for (auto it : bankMachinesOnRank)
for (auto *it : bankMachinesOnRank)
{
if (it->isActivated())
{

5
src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -49,15 +49,14 @@ class BankMachine;
class PowerDownManagerStaggered final : public PowerDownManagerIF
{
public:
PowerDownManagerStaggered(ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
Rank rank, CheckerIF& checker);
PowerDownManagerStaggered(ControllerVector<Bank, BankMachine*>& bankMachinesOnRank, Rank rank);
void triggerEntry() override;
void triggerExit() override;
void triggerInterruption() override;
CommandTuple::Type getNextCommand() override;
void update(Command) override;
void update(Command command) override;
void evaluate() override;
private:

4
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -47,8 +47,8 @@ namespace DRAMSys
RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config,
ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank)
: bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager),
memSpec(*config.memSpec), maxPostponed(static_cast<int>(config.refreshMaxPostponed)),
: memSpec(*config.memSpec), bankMachinesOnRank(bankMachinesOnRank),
powerDownManager(powerDownManager), maxPostponed(static_cast<int>(config.refreshMaxPostponed)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement)
{
timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(),

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h
View File

@@ -58,7 +58,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command command) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h
View File

@@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF
public:
CommandTuple::Type getNextCommand() override;
void evaluate() override {}
void update(Command) override {}
void update([[maybe_unused]] Command command) override {}
sc_core::sc_time getTimeForNextTrigger() override;
private:
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();

94
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp
View File

@@ -46,7 +46,7 @@ namespace DRAMSys
RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config,
ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank)
: powerDownManager(powerDownManager), memSpec(*config.memSpec),
: memSpec(*config.memSpec), powerDownManager(powerDownManager),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank / 2)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank / 2))
{
@@ -128,18 +128,17 @@ void RefreshManagerPer2Bank::evaluate()
timeForNextTrigger += memSpec.getRefreshIntervalP2B();
return;
}
else
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto *it : *currentIterator)
{
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto* it : *currentIterator)
if (it->isActivated())
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
}
// TODO: banks should already be blocked for precharge and selection should be skipped
@@ -150,54 +149,51 @@ void RefreshManagerPer2Bank::evaluate()
skipSelection = true;
}
return;
}
}
else // if (state == RmState::Pulledin)
{
bool allBankPairsBusy = true;
// if (state == RmState::Pulledin)
bool allBankPairsBusy = true;
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++)
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end();
bankIt++)
{
bool pairIsBusy = false;
for (const auto *pairIt : *bankIt)
{
bool pairIsBusy = false;
for (const auto* pairIt : *bankIt)
if (!pairIt->isIdle())
{
if (!pairIt->isIdle())
{
pairIsBusy = true;
break;
}
}
if (!pairIsBusy)
{
allBankPairsBusy = false;
currentIterator = bankIt;
pairIsBusy = true;
break;
}
}
if (allBankPairsBusy)
if (!pairIsBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalP2B();
return;
}
else
{
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto* it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
}
return;
allBankPairsBusy = false;
currentIterator = bankIt;
break;
}
}
if (allBankPairsBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalP2B();
return;
}
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads.at(currentIterator->front());
for (auto *it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads.at(it);
break;
}
}
return;
}
}

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h
View File

@@ -60,7 +60,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command command) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

73
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -46,7 +46,7 @@ namespace DRAMSys
RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config,
ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank)
: powerDownManager(powerDownManager), memSpec(*config.memSpec),
: memSpec(*config.memSpec), powerDownManager(powerDownManager),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerRank)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerRank))
{
@@ -109,54 +109,49 @@ void RefreshManagerPerBank::evaluate()
timeForNextTrigger += memSpec.getRefreshIntervalPB();
return;
}
// TODO: bank should already be blocked for precharge and selection should be skipped
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
{
// TODO: bank should already be blocked for precharge and selection should be skipped
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
{
nextCommand = Command::REFPB;
nextCommand = Command::REFPB;
if (forcedRefresh)
{
(*currentIterator)->block();
skipSelection = true;
}
if (forcedRefresh)
{
(*currentIterator)->block();
skipSelection = true;
}
return;
}
return;
}
else // if (state == RmState::Pulledin)
// if (state == RmState::Pulledin)
bool allBanksBusy = true;
for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
{
bool allBanksBusy = true;
for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
if ((*it)->isIdle())
{
if ((*it)->isIdle())
{
currentIterator = it;
allBanksBusy = false;
break;
}
}
if (allBanksBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalPB();
return;
}
else
{
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
nextCommand = Command::REFPB;
return;
currentIterator = it;
allBanksBusy = false;
break;
}
}
if (allBanksBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec.getRefreshIntervalPB();
return;
}
if ((*currentIterator)->isActivated())
nextCommand = Command::PREPB;
else
nextCommand = Command::REFPB;
return;
}
}

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h
View File

@@ -60,7 +60,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command command) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

8
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp
View File

@@ -46,7 +46,7 @@ namespace DRAMSys
RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config,
ControllerVector<Bank, BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank)
: powerDownManager(powerDownManager), memSpec(*config.memSpec),
: memSpec(*config.memSpec), powerDownManager(powerDownManager),
maxPostponed(static_cast<int>(config.refreshMaxPostponed * memSpec.banksPerGroup)),
maxPulledin(-static_cast<int>(config.refreshMaxPulledin * memSpec.banksPerGroup)),
refreshManagement(config.refreshManagement)
@@ -65,7 +65,7 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config,
}
// allBankMachines: ((0-4-8-12-16-20-24-28), (1-5-9-13-17-21-25-29), ...)
std::list<std::vector<BankMachine *>>::iterator it = allBankMachines.begin();
auto it = allBankMachines.begin();
for (unsigned bankID = 0; bankID < memSpec.banksPerGroup; bankID++)
{
for (unsigned groupID = 0; groupID < memSpec.groupsPerRank; groupID++)
@@ -216,7 +216,7 @@ void RefreshManagerSameBank::evaluate()
currentIterator = bankIt;
break;
}
else if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT())
if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT())
{
imtCandidates.emplace_back(bankIt);
}
@@ -234,7 +234,7 @@ void RefreshManagerSameBank::evaluate()
}
return;
}
else if (!imtCandidates.empty())
if (!imtCandidates.empty())
{
// search for IMT candidates and check if all banks idle
bool allGroupsBusy = true;

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h
View File

@@ -59,7 +59,7 @@ public:
CommandTuple::Type getNextCommand() override;
void evaluate() override;
void update(Command) override;
void update(Command command) override;
sc_core::sc_time getTimeForNextTrigger() override;
private:

2
src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h
View File

@@ -48,7 +48,7 @@ namespace DRAMSys
class RespQueueFifo final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;

12
src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h
View File

@@ -43,11 +43,19 @@ namespace DRAMSys
class RespQueueIF
{
protected:
RespQueueIF(const RespQueueIF &) = default;
RespQueueIF(RespQueueIF &&) = default;
RespQueueIF &operator=(const RespQueueIF &) = default;
RespQueueIF &operator=(RespQueueIF &&) = default;
public:
virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0;
RespQueueIF() = default;
virtual ~RespQueueIF() = default;
virtual void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) = 0;
virtual tlm::tlm_generic_payload* nextPayload() = 0;
[[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() = default;
};
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h
View File

@@ -47,7 +47,7 @@ namespace DRAMSys
class RespQueueReorder final : public RespQueueIF
{
public:
void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override;
void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override;
tlm::tlm_generic_payload* nextPayload() override;
[[nodiscard]] sc_core::sc_time getTriggerTime() const override;

8
src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h
View File

@@ -43,8 +43,16 @@ namespace DRAMSys
class BufferCounterIF
{
protected:
BufferCounterIF(const BufferCounterIF &) = default;
BufferCounterIF(BufferCounterIF &&) = default;
BufferCounterIF &operator=(const BufferCounterIF &) = default;
BufferCounterIF &operator=(BufferCounterIF &&) = default;
public:
BufferCounterIF() = default;
virtual ~BufferCounterIF() = default;
[[nodiscard]] virtual bool hasBufferSpace() const = 0;
virtual void storeRequest(const tlm::tlm_generic_payload& trans) = 0;
virtual void removeRequest(const tlm::tlm_generic_payload& trans) = 0;

13
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp
View File

@@ -77,11 +77,11 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin
Bank bank = bankMachine.getBank();
if (!buffer[bank].empty())
return buffer[bank].front();
else
return nullptr;
return nullptr;
}
bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const
{
if (buffer[bank].size() >= 2)
{
@@ -92,12 +92,9 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co
return false;
}
bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const
bool SchedulerFifo::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const
{
if (buffer[bank].size() >= 2)
return true;
else
return false;
return buffer[bank].size() >= 2;
}
const std::vector<unsigned>& SchedulerFifo::getBufferDepth() const

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h
View File

@@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF
public:
explicit SchedulerFifo(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& payload) override;
void removeRequest(tlm::tlm_generic_payload& payload) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

22
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -60,19 +60,19 @@ bool SchedulerFrFcfs::hasBufferSpace() const
return bufferCounter->hasBufferSpace();
}
void SchedulerFrFcfs::storeRequest(tlm_generic_payload& trans)
void SchedulerFrFcfs::storeRequest(tlm_generic_payload& payload)
{
buffer[ControllerExtension::getBank(trans)].push_back(&trans);
bufferCounter->storeRequest(trans);
buffer[ControllerExtension::getBank(payload)].push_back(&payload);
bufferCounter->storeRequest(payload);
}
void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans)
void SchedulerFrFcfs::removeRequest(tlm_generic_payload& payload)
{
bufferCounter->removeRequest(trans);
Bank bank = ControllerExtension::getBank(trans);
bufferCounter->removeRequest(payload);
Bank bank = ControllerExtension::getBank(payload);
for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++)
{
if (*it == &trans)
if (*it == &payload)
{
buffer[bank].erase(it);
break;
@@ -89,7 +89,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach
{
// Search for row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : buffer[bank])
for (auto* it : buffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
@@ -101,10 +101,10 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach
return nullptr;
}
bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const
{
unsigned rowHitCounter = 0;
for (auto it : buffer[bank])
for (auto* it : buffer[bank])
{
if (ControllerExtension::getRow(*it) == row)
{
@@ -116,7 +116,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command)
return false;
}
bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const
bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const
{
return (buffer[bank].size() >= 2);
}

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF
public:
explicit SchedulerFrFcfs(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& payload) override;
void removeRequest(tlm::tlm_generic_payload& payload) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

13
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -91,7 +91,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM
// Filter all row hits
Row openRow = bankMachine.getOpenRow();
std::list<tlm_generic_payload *> rowHits;
for (auto it : buffer[bank])
for (auto *it : buffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
rowHits.push_back(it);
@@ -126,10 +126,10 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM
return nullptr;
}
bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const
{
unsigned rowHitCounter = 0;
for (auto it : buffer[bank])
for (auto *it : buffer[bank])
{
if (ControllerExtension::getRow(*it) == row)
{
@@ -141,12 +141,9 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman
return false;
}
bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const
bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const
{
if (buffer[bank].size() >= 2)
return true;
else
return false;
return buffer[bank].size() >= 2;
}
const std::vector<unsigned>& SchedulerFrFcfsGrp::getBufferDepth() const

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF
public:
explicit SchedulerFrFcfsGrp(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& payload) override;
void removeRequest(tlm::tlm_generic_payload& payload) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

132
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp
View File

@@ -63,25 +63,25 @@ bool SchedulerGrpFrFcfs::hasBufferSpace() const
return bufferCounter->hasBufferSpace();
}
void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& trans)
void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& payload)
{
if (trans.is_read())
readBuffer[ControllerExtension::getBank(trans)].push_back(&trans);
if (payload.is_read())
readBuffer[ControllerExtension::getBank(payload)].push_back(&payload);
else
writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans);
bufferCounter->storeRequest(trans);
writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload);
bufferCounter->storeRequest(payload);
}
void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans)
void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& payload)
{
bufferCounter->removeRequest(trans);
lastCommand = trans.get_command();
Bank bank = ControllerExtension::getBank(trans);
bufferCounter->removeRequest(payload);
lastCommand = payload.get_command();
Bank bank = ControllerExtension::getBank(payload);
if (trans.is_read())
readBuffer[bank].remove(&trans);
if (payload.is_read())
readBuffer[bank].remove(&payload);
else
writeBuffer[bank].remove(&trans);
writeBuffer[bank].remove(&payload);
}
tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankMachine) const
@@ -98,7 +98,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : readBuffer[bank])
for (auto *it : readBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
@@ -107,33 +107,13 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM
// No read row hit found or bank precharged
return readBuffer[bank].front();
}
else if (!writeBuffer[bank].empty())
{
if (bankMachine.isActivated())
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : writeBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No write row hit found or bank precharged
return writeBuffer[bank].front();
}
else
return nullptr;
}
else
{
if (!writeBuffer[bank].empty())
{
if (bankMachine.isActivated())
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : writeBuffer[bank])
for (auto *it : writeBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
@@ -142,24 +122,40 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM
// No write row hit found or bank precharged
return writeBuffer[bank].front();
}
else if (!readBuffer[bank].empty())
{
if (bankMachine.isActivated())
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : readBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No read row hit found or bank precharged
return readBuffer[bank].front();
}
else
return nullptr;
return nullptr;
}
if (!writeBuffer[bank].empty())
{
if (bankMachine.isActivated())
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : writeBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No write row hit found or bank precharged
return writeBuffer[bank].front();
}
if (!readBuffer[bank].empty())
{
if (bankMachine.isActivated())
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto *it : readBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
}
// No read row hit found or bank precharged
return readBuffer[bank].front();
}
return nullptr;
}
bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
@@ -168,7 +164,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman
unsigned rowHitCounter = 0;
if (command == tlm::TLM_READ_COMMAND)
{
for (auto it : readBuffer[bank])
for (auto *it : readBuffer[bank])
{
if (ControllerExtension::getRow(*it) == row)
{
@@ -179,37 +175,29 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman
}
return false;
}
else
for (auto* it : writeBuffer[bank])
{
for (auto it : writeBuffer[bank])
if (ControllerExtension::getRow(*it) == row)
{
if (ControllerExtension::getRow(*it) == row)
{
rowHitCounter++;
if (rowHitCounter == 2)
return true;
}
rowHitCounter++;
if (rowHitCounter == 2)
return true;
}
return false;
}
return false;
}
bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const
{
if (command == tlm::TLM_READ_COMMAND)
{
if (readBuffer[bank].size() >= 2)
return true;
else
return false;
}
else
{
if (writeBuffer[bank].size() >= 2)
return true;
else
return false;
return readBuffer[bank].size() >= 2;
}
return writeBuffer[bank].size() >= 2;
}
const std::vector<unsigned>& SchedulerGrpFrFcfs::getBufferDepth() const

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h
View File

@@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF
public:
explicit SchedulerGrpFrFcfs(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& payload) override;
void removeRequest(tlm::tlm_generic_payload& payload) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

80
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp
View File

@@ -67,25 +67,25 @@ bool SchedulerGrpFrFcfsWm::hasBufferSpace() const
return bufferCounter->hasBufferSpace();
}
void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans)
void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& payload)
{
if (trans.is_read())
readBuffer[ControllerExtension::getBank(trans)].push_back(&trans);
if (payload.is_read())
readBuffer[ControllerExtension::getBank(payload)].push_back(&payload);
else
writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans);
bufferCounter->storeRequest(trans);
writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload);
bufferCounter->storeRequest(payload);
evaluateWriteMode();
}
void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans)
void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& payload)
{
bufferCounter->removeRequest(trans);
Bank bank = ControllerExtension::getBank(trans);
bufferCounter->removeRequest(payload);
Bank bank = ControllerExtension::getBank(payload);
if (trans.is_read())
readBuffer[bank].remove(&trans);
if (payload.is_read())
readBuffer[bank].remove(&payload);
else
writeBuffer[bank].remove(&trans);
writeBuffer[bank].remove(&payload);
evaluateWriteMode();
}
@@ -102,7 +102,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban
{
// Search for read row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : readBuffer[bank])
for (auto *it : readBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
@@ -111,32 +111,29 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban
// No read row hit found or bank precharged
return readBuffer[bank].front();
}
else
return nullptr;
return nullptr;
}
else
if (!writeBuffer[bank].empty())
{
if (!writeBuffer[bank].empty())
if (bankMachine.isActivated())
{
if (bankMachine.isActivated())
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto* it : writeBuffer[bank])
{
// Search for write row hit
Row openRow = bankMachine.getOpenRow();
for (auto it : writeBuffer[bank])
{
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
if (ControllerExtension::getRow(*it) == openRow)
return it;
}
// No row hit found or bank precharged
return writeBuffer[bank].front();
}
else
return nullptr;
// No row hit found or bank precharged
return writeBuffer[bank].front();
}
return nullptr;
}
bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const
bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm::tlm_command command) const
{
unsigned rowHitCounter = 0;
if (!writeMode)
@@ -152,27 +149,28 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command
}
return false;
}
else
for (auto* it : writeBuffer[bank])
{
for (auto it : writeBuffer[bank])
if (ControllerExtension::getRow(*it) == row)
{
if (ControllerExtension::getRow(*it) == row)
{
rowHitCounter++;
if (rowHitCounter == 2)
return true;
}
rowHitCounter++;
if (rowHitCounter == 2)
return true;
}
return false;
}
return false;
}
bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const
bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm::tlm_command command) const
{
if (!writeMode)
{
return (readBuffer[bank].size() >= 2);
else
return (writeBuffer[bank].size() >= 2);
}
return (writeBuffer[bank].size() >= 2);
}
const std::vector<unsigned>& SchedulerGrpFrFcfsWm::getBufferDepth() const

10
src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h
View File

@@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF
public:
explicit SchedulerGrpFrFcfsWm(const Configuration& config);
[[nodiscard]] bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload&) override;
void removeRequest(tlm::tlm_generic_payload&) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override;
void storeRequest(tlm::tlm_generic_payload& payload) override;
void removeRequest(tlm::tlm_generic_payload& payload) override;
[[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override;
[[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override;
[[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override;
[[nodiscard]] const std::vector<unsigned>& getBufferDepth() const override;
private:

18
src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h
View File

@@ -47,14 +47,22 @@ class BankMachine;
class SchedulerIF
{
protected:
SchedulerIF(const SchedulerIF &) = default;
SchedulerIF(SchedulerIF &&) = default;
SchedulerIF &operator=(const SchedulerIF &) = default;
SchedulerIF &operator=(SchedulerIF &&) = default;
public:
SchedulerIF() = default;
virtual ~SchedulerIF() = default;
[[nodiscard]] virtual bool hasBufferSpace() const = 0;
virtual void storeRequest(tlm::tlm_generic_payload&) = 0;
virtual void removeRequest(tlm::tlm_generic_payload&) = 0;
[[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const = 0;
[[nodiscard]] virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0;
[[nodiscard]] virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0;
virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0;
virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0;
[[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const = 0;
[[nodiscard]] virtual bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0;
[[nodiscard]] virtual bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const = 0;
[[nodiscard]] virtual const std::vector<unsigned>& getBufferDepth() const = 0;
};

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