diff --git a/.clang-format b/.clang-format new file mode 100755 index 00000000..afdb4719 --- /dev/null +++ b/.clang-format @@ -0,0 +1,11 @@ +AccessModifierOffset: '-4' +AllowShortFunctionsOnASingleLine: InlineOnly +AllowShortIfStatementsOnASingleLine: Never +BinPackArguments: 'false' +BinPackParameters: 'false' +BreakBeforeBraces: Allman +BreakConstructorInitializers: AfterColon +ColumnLimit: '100' +ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' +IndentWidth: '4' +PointerAlignment: Left diff --git a/.clang-tidy b/.clang-tidy new file mode 100644 index 00000000..15cccef3 --- /dev/null +++ b/.clang-tidy @@ -0,0 +1,18 @@ +Checks: > + clang-diagnostic-*, + clang-analyzer-*, + modernize-*, + bugprone-*, + concurrency-*, + cppcoreguidelines-*, + performance-*, + portability-*, + readability-*, + -modernize-use-trailing-return-type, + -readability-braces-around-statements, + -readability-identifier-length, + -readability-function-cognitive-complexity +WarningsAsErrors: '' +HeaderFilterRegex: '' +AnalyzeTemporaryDtors: false +FormatStyle: file diff --git a/CMakePresets.json b/CMakePresets.json index 6acf65ad..3bd3c6fc 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -69,7 +69,8 @@ "std" ], "cacheVariables": { - "CMAKE_BUILD_TYPE": "Debug" + "CMAKE_BUILD_TYPE": "Debug", + "CMAKE_CXX_FLAGS": "-Wall -Wextra -Wpedantic" } } ] diff --git a/extensions/apps/traceAnalyzer/.clang-format b/extensions/apps/traceAnalyzer/.clang-format deleted file mode 100644 index 950e9ea8..00000000 --- a/extensions/apps/traceAnalyzer/.clang-format +++ /dev/null @@ -1,13 +0,0 @@ ---- -BasedOnStyle: LLVM -AccessModifierOffset: '-4' -AllowShortFunctionsOnASingleLine: None -AllowShortIfStatementsOnASingleLine: Never -AllowShortLoopsOnASingleLine: 'false' -AlwaysBreakTemplateDeclarations: 'true' -BreakBeforeBraces: Allman -ColumnLimit: '120' -IndentWidth: '4' -PointerAlignment: Right - -... diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 66144e80..6793d0f9 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -59,30 +59,30 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")), tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), tRL (tCK * memSpec.memtimingspec.entries.at("RL")), + //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), + tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), //tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), //tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), tWL (tCK * memSpec.memtimingspec.entries.at("WL")), + tWR (tCK * memSpec.memtimingspec.entries.at("WR")), //tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), //tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), //tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), //tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), //tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), @@ -104,10 +104,10 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), tBURST16(tCK * 16 / dataRate), tBURST32(tCK * 32 / dataRate), - bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)) + bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { commandLengthInCycles[Command::ACT] = 2; diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index 8e90dec4..7909bf61 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -124,9 +124,8 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector if (file.is_open()) { json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY); return simulation.get(); - } else { - throw std::runtime_error("Failed to open file " + std::string(path)); } + throw std::runtime_error("Failed to open file " + std::string(path)); } } // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/TraceSetup.h b/src/configuration/DRAMSys/config/TraceSetup.h index 9d7a5055..f59629d1 100644 --- a/src/configuration/DRAMSys/config/TraceSetup.h +++ b/src/configuration/DRAMSys/config/TraceSetup.h @@ -70,7 +70,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid struct TracePlayer { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -81,10 +81,10 @@ NLOHMANN_JSONIFY_ALL_THINGS( struct TrafficGeneratorActiveState { - unsigned int id; + unsigned int id{}; - uint64_t numRequests; - double rwRatio; + uint64_t numRequests{}; + double rwRatio{}; AddressDistribution addressDistribution; std::optional addressIncrement; std::optional minAddress; @@ -120,7 +120,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probabili struct TrafficGenerator { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -130,8 +130,8 @@ struct TrafficGenerator std::optional dataLength; std::optional dataAlignment; - uint64_t numRequests; - double rwRatio; + uint64_t numRequests{}; + double rwRatio{}; AddressDistribution addressDistribution; std::optional addressIncrement; std::optional minAddress; @@ -156,7 +156,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator, struct TrafficGeneratorStateMachine { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -183,13 +183,13 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine, struct RowHammer { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; - uint64_t numRequests; - uint64_t rowIncrement; + uint64_t numRequests{}; + uint64_t rowIncrement{}; }; NLOHMANN_JSONIFY_ALL_THINGS( diff --git a/src/libdramsys/DRAMSys/common/DebugManager.cpp b/src/libdramsys/DRAMSys/common/DebugManager.cpp index f558057b..0bd0de25 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.cpp +++ b/src/libdramsys/DRAMSys/common/DebugManager.cpp @@ -74,10 +74,7 @@ void DebugManager::openDebugFile(const std::string &filename) debugFile.open(filename); } -DebugManager::DebugManager() - : debugEnabled(false), writeToConsole(false), writeToFile(false) -{ -} +DebugManager::DebugManager() = default; DebugManager::~DebugManager() { diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index 411183b2..0c93e050 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -64,8 +64,9 @@ private: public: DebugManager(const DebugManager&) = delete; DebugManager& operator=(const DebugManager&) = delete; + DebugManager(DebugManager&&) = delete; + DebugManager& operator=(DebugManager&&) = delete; -public: void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); void printDebugMessage(const std::string &sender, const std::string &message); @@ -73,9 +74,9 @@ public: void openDebugFile(const std::string &filename); private: - bool debugEnabled; - bool writeToConsole; - bool writeToFile; + bool debugEnabled = false; + bool writeToConsole = false; + bool writeToFile = false; std::ofstream debugFile; }; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index c55b9392..a0b6410d 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -52,18 +52,21 @@ using namespace tlm; namespace DRAMSys { -TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) : - name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0), - simulationTimeCoveredByRecording(SC_ZERO_TIME) +TlmRecorder::TlmRecorder(const std::string &name, + const Configuration &config, + const std::string &dbName) : + name(name), + config(config), + memSpec(*config.memSpec), + currentDataBuffer(&recordingDataBuffer.at(0)), + storageDataBuffer(&recordingDataBuffer.at(1)), + simulationTimeCoveredByRecording(SC_ZERO_TIME) { - currentDataBuffer = &recordingDataBuffer[0]; - storageDataBuffer = &recordingDataBuffer[1]; - currentDataBuffer->reserve(transactionCommitRate); storageDataBuffer->reserve(transactionCommitRate); openDB(dbName); - char *sErrMsg; + char *sErrMsg = nullptr; sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.locking_mode=EXCLUSIVE", nullptr, nullptr, &sErrMsg); @@ -81,7 +84,7 @@ TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, c void TlmRecorder::finalize() { - if (db) + if (db != nullptr) closeConnection(); sqlite3_finalize(insertTransactionStatement); sqlite3_finalize(insertRangeStatement); @@ -149,7 +152,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase } else if (isFixedCommandPhase(phase)) { - tlm_generic_payload* keyTrans; + tlm_generic_payload* keyTrans = nullptr; if (ChildExtension::isChildTrans(trans)) { keyTrans = &ChildExtension::getParentTrans(trans); @@ -213,7 +216,7 @@ void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans) { totalNumTransactions++; - char commandChar; + char commandChar = 0; tlm_command command = trans.get_command(); if (command == TLM_READ_COMMAND) commandChar = 'R'; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 0164ed32..e5de03e4 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -63,8 +63,11 @@ class TlmRecorder { public: TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName); - TlmRecorder(const TlmRecorder&) = delete; - TlmRecorder(TlmRecorder&&) = default; + TlmRecorder(const TlmRecorder &) = delete; + TlmRecorder(TlmRecorder &&) = default; + TlmRecorder &operator=(const TlmRecorder &) = delete; + TlmRecorder &operator=(TlmRecorder &&) = delete; + ~TlmRecorder() = default; void recordMcConfig(std::string _mcconfig) { @@ -89,12 +92,12 @@ public: void finalize(); private: + std::string name; const Configuration& config; const MemSpec& memSpec; struct Transaction { - Transaction(const Transaction& other) = default; Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), @@ -131,8 +134,6 @@ private: std::vector recordedPhases; }; - std::string name; - std::string mcconfig, memspec, traces; void prepareSqlStatements(); @@ -162,7 +163,7 @@ private: std::unordered_map currentTransactionsInSystem; - uint64_t totalNumTransactions; + uint64_t totalNumTransactions = 0; sc_core::sc_time simulationTimeCoveredByRecording; sqlite3 *db = nullptr; diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.cpp b/src/libdramsys/DRAMSys/common/dramExtensions.cpp index 0ec5f106..2e2bf907 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.cpp +++ b/src/libdramsys/DRAMSys/common/dramExtensions.cpp @@ -310,10 +310,7 @@ void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans) { - if (trans.get_extension() != nullptr) - return true; - else - return false; + return trans.get_extension() != nullptr; } tlm_extension_base* ParentExtension::clone() const @@ -358,10 +355,8 @@ bool ParentExtension::notifyChildTransCompletion() childTranses.clear(); return true; } - else - { - return false; - } + + return false; } bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans) diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 4e273f12..63765b8d 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -87,13 +87,13 @@ public: static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - Thread getThread() const; - Channel getChannel() const; - uint64_t getThreadPayloadID() const; - sc_core::sc_time getTimeOfGeneration() const; + [[nodiscard]] Thread getThread() const; + [[nodiscard]] Channel getChannel() const; + [[nodiscard]] uint64_t getThreadPayloadID() const; + [[nodiscard]] sc_core::sc_time getTimeOfGeneration() const; static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans); static Thread getThread(const tlm::tlm_generic_payload& trans); @@ -120,16 +120,16 @@ public: //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - uint64_t getChannelPayloadID() const; - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getRow() const; - Column getColumn() const; - unsigned getBurstLength() const; + [[nodiscard]] uint64_t getChannelPayloadID() const; + [[nodiscard]] Rank getRank() const; + [[nodiscard]] BankGroup getBankGroup() const; + [[nodiscard]] Bank getBank() const; + [[nodiscard]] Row getRow() const; + [[nodiscard]] Column getColumn() const; + [[nodiscard]] unsigned getBurstLength() const; static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); @@ -161,7 +161,7 @@ private: public: //ChildExtension() = delete; - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; tlm::tlm_generic_payload& getParentTrans(); static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans); @@ -180,7 +180,7 @@ private: public: ParentExtension() = delete; - tlm_extension_base* clone() const override; + [[nodiscard]] tlm_extension_base* clone() const override; void copy_from(const tlm_extension_base& ext) override; static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); const std::vector& getChildTranses(); @@ -191,15 +191,12 @@ public: class EccExtension : public tlm::tlm_extension { public: - tlm_extension_base* clone() const override + [[nodiscard]] tlm_extension_base* clone() const override { return new EccExtension; } - void copy_from(tlm_extension_base const &ext) override - { - auto const &cpyFrom = static_cast(ext); - } + void copy_from([[maybe_unused]] tlm_extension_base const & ext) override {} }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index 7eaf2ff6..3eb03d4a 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -60,10 +60,10 @@ bool TimeInterval::intersects(const TimeInterval &other) const sc_time TimeInterval::getLength() const { - if (end > start) - return end - start; - else + if (start > end) return start - end; + + return end - start; } std::string getPhaseName(const tlm_phase &phase) diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index a6f922be..85d2da3e 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -56,12 +56,12 @@ public: TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {} TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {} - sc_core::sc_time getLength() const; - bool timeIsInInterval(const sc_core::sc_time &time) const; - bool intersects(const TimeInterval &other) const; + [[nodiscard]] sc_core::sc_time getLength() const; + [[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const; + [[nodiscard]] bool intersects(const TimeInterval &other) const; }; -constexpr const char headline[] = +constexpr const std::string_view headline = "==========================================================================="; std::string getPhaseName(const tlm::tlm_phase &phase); diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index 3eca6cbf..b13d4bc6 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -71,21 +71,25 @@ enum sc_time_unit string2TimeUnit(const std::string &s) { if (s == "s") return SC_SEC; - else if (s == "ms") + + if (s == "ms") return SC_MS; - else if (s == "us") + + if (s == "us") return SC_US; - else if (s == "ns") + + if (s == "ns") return SC_NS; - else if (s == "ps") + + if (s == "ps") return SC_PS; - else if (s == "fs") + + if (s == "fs") return SC_FS; - else { - SC_REPORT_FATAL("Configuration", - ("Could not convert to enum sc_time_unit: " + s).c_str()); - throw; - } + + SC_REPORT_FATAL("Configuration", + ("Could not convert to enum sc_time_unit: " + s).c_str()); + throw; } void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index 017ef610..55700028 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -54,11 +54,6 @@ namespace DRAMSys class Configuration { -public: - Configuration() = default; - Configuration(const Configuration&) = delete; - Configuration& operator=(const Configuration &) = delete; - public: // MCConfig: enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index 7fc5b70d..f02db58b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -75,8 +75,8 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec, tCK(sc_time(1.0 / fCKMHz, SC_US)), memoryId(memSpec.memoryId), memoryType(memoryType), - burstDuration(tCK* (static_cast(defaultBurstLength) / dataRate)), - memorySizeBytes(0) + burstDuration(tCK* (static_cast(defaultBurstLength) / dataRate)) + { commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); } diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 7b28e7ac..d87c0841 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -54,6 +54,10 @@ namespace DRAMSys class MemSpec { public: + MemSpec &operator=(const MemSpec &) = delete; + MemSpec &operator=(MemSpec &&) = delete; + virtual ~MemSpec() = default; + const unsigned numberOfChannels; const unsigned pseudoChannelsPerChannel; const unsigned ranksPerChannel; @@ -84,29 +88,26 @@ public: WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, HBM3, STTMRAM } memoryType; - virtual ~MemSpec() = default; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalSB() const; - virtual sc_core::sc_time getRefreshIntervalAB() const; - virtual sc_core::sc_time getRefreshIntervalPB() const; - virtual sc_core::sc_time getRefreshIntervalP2B() const; - virtual sc_core::sc_time getRefreshIntervalSB() const; + [[nodiscard]] virtual unsigned getPer2BankOffset() const; - virtual unsigned getPer2BankOffset() const; + [[nodiscard]] virtual unsigned getRAAIMT() const; + [[nodiscard]] virtual unsigned getRAAMMT() const; + [[nodiscard]] virtual unsigned getRAADEC() const; - virtual unsigned getRAAIMT() const; - virtual unsigned getRAAMMT() const; - virtual unsigned getRAADEC() const; + [[nodiscard]] virtual bool hasRasAndCasBus() const; - virtual bool hasRasAndCasBus() const; + [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const; - virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - - virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const; - - sc_core::sc_time getCommandLength(Command) const; - double getCommandLengthInCycles(Command) const; - uint64_t getSimMemSizeInBytes() const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const; + [[nodiscard]] double getCommandLengthInCycles(Command command) const; + [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: MemSpec(const DRAMSys::Config::MemSpec& memSpec, @@ -117,10 +118,13 @@ protected: unsigned banksPerChannel, unsigned bankGroupsPerChannel, unsigned devicesPerRank); + MemSpec(const MemSpec &) = default; + MemSpec(MemSpec &&) = default; + // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; sc_core::sc_time burstDuration; - uint64_t memorySizeBytes; + uint64_t memorySizeBytes = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 716f44e1..61c3a347 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -61,7 +61,6 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,16 +70,17 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), + tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), @@ -127,41 +127,45 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index a9db6433..f903de1d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -93,10 +93,10 @@ public: const double iDD3P0; const double iDD3P1; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index d781c42e..a99844be 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -146,41 +146,44 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 2849faca..1cf895d8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -100,10 +100,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 1bb1f1b7..18952687 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index b9748814..7b1da4c2 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 5d380a2b..fa64ee7e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 8c428d10..87ad3570 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index d8ff81a0..9339abe4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -60,7 +60,6 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), @@ -96,7 +95,8 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")), tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")), tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; @@ -143,44 +143,48 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB || command == Command::REFP2B) + + if (command == Command::REFPB || command == Command::REFP2B) return tRFCpb; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index c45595d9..a216fca8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -91,13 +91,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getRefreshIntervalP2B() const override; - unsigned getPer2BankOffset() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override; + [[nodiscard]] unsigned getPer2BankOffset() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 61acd0f6..e76d4d1f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -131,44 +131,48 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCSB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index 2ccba274..b4c681c8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -85,13 +85,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - bool hasRasAndCasBus() const override; + [[nodiscard]] bool hasRasAndCasBus() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index bcdf6124..9c5597ff 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -62,12 +62,12 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), @@ -135,45 +135,50 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb + tCK; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab + tCK; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD + 3 * tCK; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration + 3 * tCK; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRTP - 5 * tCK + tRPpb; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + 4 * tCK + burstDuration + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab + tCK; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb + tCK; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK}; - else - { - SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 9025a87f..931300f8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -87,11 +87,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index 46071ad9..0819d78f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -61,7 +61,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,14 +70,15 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), + tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) @@ -104,39 +104,41 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tWR + tRP; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; } -TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const +TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index 7cb862ad..dd2e09d9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -78,8 +78,8 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index cae6509c..f0fcb503 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -60,8 +60,6 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfDevices")), tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tAC (tCK * memSpec.memtimingspec.entries.at("AC")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -70,11 +68,13 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), - tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tAC (tCK * memSpec.memtimingspec.entries.at("AC")), + tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), + tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), @@ -133,41 +133,44 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tAC + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRP; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration - tCK + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index d8e0042f..5f62b761 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -98,10 +98,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index 42352afc..55cc06db 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -117,45 +117,50 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration - 2 * tCK + tRTP + tRPpb; - else if (command == Command::WR || command == Command::MWR) + + if (command == Command::WR || command == Command::MWR) return tWL + tDQSS + burstDuration; - else if (command == Command::WRA || command == Command::MWRA) + + if (command == Command::WRA || command == Command::MWRA) return tWL + burstDuration + tCK + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb; - else - { - SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + + if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) return {tWL + tDQSS, tWL + tDQSS + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 8547e640..3b418b62 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -79,11 +79,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 95529068..e6ba0643 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -44,12 +44,15 @@ using namespace tlm; namespace DRAMSys { -BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : scheduler(scheduler), memSpec(*config.memSpec), bank(bank), +BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) : + memSpec(*config.memSpec), + scheduler(scheduler), + bank(bank), bankgroup(BankGroup(static_cast(bank) / memSpec.banksPerGroup)), rank(Rank(static_cast(bank) / memSpec.banksPerRank)), refreshManagement(config.refreshManagement) -{} +{ +} CommandTuple::Type BankMachine::getNextCommand() { @@ -172,41 +175,37 @@ void BankMachineOpen::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) + { + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; + else { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; - } + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; } - else // row miss - nextCommand = Command::PREPB; } + else // row miss + nextCommand = Command::PREPB; } } } @@ -220,35 +219,31 @@ void BankMachineClosed::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) + { + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; - } + currentPayload = newPayload; + } + + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; else { - currentPayload = newPayload; - } - - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; - } + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } } @@ -263,55 +258,51 @@ void BankMachineOpenAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) + { + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit + if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) && + !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { - if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) - && !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; - } - } + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; else { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; - } + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + } + } + else + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; + else + { + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; } } - else // row miss - nextCommand = Command::PREPB; } + else // row miss + nextCommand = Command::PREPB; } } } @@ -326,54 +317,50 @@ void BankMachineClosedAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) + { + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit + if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { - if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; - } - } + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; else { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; - } + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + } + } + else + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; + else + { + nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } - else // row miss, can happen when RD/WR mode is switched - nextCommand = Command::PREPB; } + else // row miss, can happen when RD/WR mode is switched + nextCommand = Command::PREPB; } } } diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 23ff09e9..8dd4ab1a 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -53,7 +53,7 @@ class BankMachine : public ManagerIF { public: CommandTuple::Type getNextCommand() override; - void update(Command) override; + void update(Command command) override; void block(); [[nodiscard]] Rank getRank() const; diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 1e43035e..26d39df3 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -86,7 +86,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 28 DECLARE_EXTENDED_PHASE(END_SREF); // 29 #ifdef DRAMPOWER -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); #endif bool phaseHasDataStrobe(tlm::tlm_phase phase); diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 30f5b647..74ff6042 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -80,10 +80,10 @@ namespace DRAMSys { Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : - ControllerIF(name, config), addressDecoder(addressDecoder), - thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), - phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw), - blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay), + ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), + thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), + phyDelayBw(config.phyDelayBw), blockingReadDelay(config.blockingReadDelay), + blockingWriteDelay(config.blockingWriteDelay), addressDecoder(addressDecoder), minBytesPerBurst(config.memSpec->defaultBytesPerBurst), maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { @@ -207,8 +207,8 @@ Controller::Controller(const sc_module_name& name, const Configuration& config, { for (unsigned rankID = 0; rankID < memSpec.ranksPerChannel; rankID++) { - powerDownManagers.push_back(std::make_unique(bankMachinesOnRank[Rank(rankID)], - Rank(rankID), *checker)); + powerDownManagers.push_back(std::make_unique( + bankMachinesOnRank[Rank(rankID)], Rank(rankID))); } } @@ -293,7 +293,7 @@ void Controller::controllerMethod() readyCommands.emplace_back(commandTuple); // (4.3) Check for bank commands (PREPB, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rank]) + for (auto* it : bankMachinesOnRank[rank]) { commandTuple = it->getNextCommand(); if (std::get(commandTuple) != Command::NOP) @@ -322,7 +322,7 @@ void Controller::controllerMethod() if (command.isRankCommand()) { - for (auto it : bankMachinesOnRank[rank]) + for (auto* it : bankMachinesOnRank[rank]) it->update(command); } else if (command.isGroupCommand()) @@ -442,7 +442,9 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&) +tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; @@ -623,12 +625,10 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate() { return *new tlm_generic_payload(this); } - else - { - tlm_generic_payload* result = freePayloads.top(); - freePayloads.pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads.top(); + freePayloads.pop(); + return *result; } void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans) diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index 7fa929bf..0a472d72 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -116,7 +116,13 @@ private: class MemoryManager : public tlm::tlm_mm_interface { public: + MemoryManager() = default; + MemoryManager(const MemoryManager &) = delete; + MemoryManager(MemoryManager &&) = delete; + MemoryManager &operator=(const MemoryManager &) = delete; + MemoryManager &operator=(MemoryManager &&) = delete; ~MemoryManager() override; + tlm::tlm_generic_payload& allocate(); void free(tlm::tlm_generic_payload* trans) override; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index 056ab541..d82ba70f 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -45,8 +45,8 @@ namespace DRAMSys ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), - activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing), - windowSizeTime(config.windowSize * memSpec.tCK) + windowSizeTime(config.windowSize * memSpec.tCK), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), + enableWindowing(config.enableWindowing) { if (enableWindowing) { @@ -65,8 +65,9 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&, - tlm_phase&, sc_time&) +tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 727cadb6..0445179c 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -49,7 +49,6 @@ class ControllerRecordable final : public Controller public: ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder); - ~ControllerRecordable() override = default; protected: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, @@ -57,7 +56,8 @@ protected: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; + void sendToFrontend(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; void controllerMethod() override; diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 65b4c4db..b4e1c380 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -42,11 +42,19 @@ namespace DRAMSys class ManagerIF { +protected: + ManagerIF(const ManagerIF &) = default; + ManagerIF(ManagerIF &&) = default; + ManagerIF &operator=(const ManagerIF &) = default; + ManagerIF &operator=(ManagerIF &&) = default; + public: + ManagerIF() = default; + virtual ~ManagerIF() = default; + virtual void evaluate() = 0; virtual CommandTuple::Type getNextCommand() = 0; - virtual void update(Command) = 0; - virtual ~ManagerIF() = default; + virtual void update(Command command) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp index 48b51ae1..d717c74d 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerDDR3::CheckerDDR3(const Configuration& config) +CheckerDDR3::CheckerDDR3(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h index be4a0273..bb9bed97 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h @@ -49,7 +49,7 @@ class CheckerDDR3 final : public CheckerIF { public: explicit CheckerDDR3(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp index be50f739..ebfb8a98 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerDDR4::CheckerDDR4(const Configuration& config) +CheckerDDR4::CheckerDDR4(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h index cde5690c..c805d71d 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h @@ -51,7 +51,7 @@ class CheckerDDR4 final : public CheckerIF { public: explicit CheckerDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp index b6258fcf..a4af51c8 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR5::CheckerGDDR5(const Configuration& config) +CheckerGDDR5::CheckerGDDR5(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h index 59e965ba..ebbde0b4 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h @@ -49,7 +49,7 @@ class CheckerGDDR5 final : public CheckerIF { public: explicit CheckerGDDR5(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp index f2f1d283..73998716 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) +CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h index c3d664c4..5c619b25 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h @@ -49,7 +49,7 @@ class CheckerGDDR5X final : public CheckerIF { public: explicit CheckerGDDR5X(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp index f86d71f2..b8284962 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR6::CheckerGDDR6(const Configuration& config) +CheckerGDDR6::CheckerGDDR6(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h index 5446f520..acdbcdef 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h @@ -49,7 +49,7 @@ class CheckerGDDR6 final : public CheckerIF { public: explicit CheckerGDDR6(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp index 3969fd84..f795b54a 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerHBM2::CheckerHBM2(const Configuration& config) +CheckerHBM2::CheckerHBM2(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h index 66e7e537..fa83f280 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h @@ -49,7 +49,7 @@ class CheckerHBM2 final : public CheckerIF { public: explicit CheckerHBM2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index df8bb8b1..6580e910 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -44,10 +44,17 @@ namespace DRAMSys class CheckerIF { +protected: + CheckerIF(const CheckerIF &) = default; + CheckerIF(CheckerIF &&) = default; + CheckerIF &operator=(const CheckerIF &) = default; + CheckerIF &operator=(CheckerIF &&) = default; + public: + CheckerIF() = default; virtual ~CheckerIF() = default; - virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0; }; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index 7c920ae1..1e8ea005 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) +CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h index 965ef8fc..58d6e2f6 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h @@ -49,7 +49,7 @@ class CheckerLPDDR4 final : public CheckerIF { public: explicit CheckerLPDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp index ff1535bd..24006e50 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) +CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h index eb2ab813..f8df0551 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h @@ -49,7 +49,7 @@ class CheckerSTTMRAM final : public CheckerIF { public: explicit CheckerSTTMRAM(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp index a9912809..a7c861fa 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerWideIO::CheckerWideIO(const Configuration& config) +CheckerWideIO::CheckerWideIO(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h index 0a2c7032..774ec9f3 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h @@ -49,7 +49,7 @@ class CheckerWideIO final : public CheckerIF { public: explicit CheckerWideIO(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp index aa1c54cf..ebf51586 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerWideIO2::CheckerWideIO2(const Configuration& config) +CheckerWideIO2::CheckerWideIO2(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h index d787870b..86ada7d4 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h @@ -49,7 +49,7 @@ class CheckerWideIO2 final : public CheckerIF { public: explicit CheckerWideIO2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index 8f02c1bc..c032a159 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -42,9 +42,17 @@ namespace DRAMSys class CmdMuxIF { +protected: + CmdMuxIF(const CmdMuxIF &) = default; + CmdMuxIF(CmdMuxIF &&) = default; + CmdMuxIF &operator=(const CmdMuxIF &) = default; + CmdMuxIF &operator=(CmdMuxIF &&) = default; + public: + CmdMuxIF() = default; virtual ~CmdMuxIF() = default; - virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0; + + virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index 89487f9d..830e049f 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand { auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -73,8 +73,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -103,7 +102,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC auto resultCas = readyCasCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -179,8 +178,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index e8a24502..6ff5772c 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF { public: explicit CmdMuxOldest(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; @@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF { public: explicit CmdMuxOldestRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index ec288a90..15627c42 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand { auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -83,8 +83,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand nextPayloadID++; return *result; } - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -113,7 +112,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC auto resultCas = readyCasCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -181,8 +180,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC if (std::get(*result).isCasCommand()) nextPayloadID++; return *result; - } - else + } return {Command::NOP, nullptr, scMaxTime}; } diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index b69f1aa7..2b98bc9e 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF { public: explicit CmdMuxStrict(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; @@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: explicit CmdMuxStrictRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index 07604fb4..8e81f472 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -50,7 +50,7 @@ public: void triggerInterruption() override {} CommandTuple::Type getNextCommand() override; - void update(Command) override {} + void update([[maybe_unused]] Command command) override {} void evaluate() override {} }; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index a9d0213d..f380d508 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -42,9 +42,9 @@ using namespace tlm; namespace DRAMSys { -PowerDownManagerStaggered::PowerDownManagerStaggered(ControllerVector& bankMachinesOnRank, - Rank rank, CheckerIF& checker) - : bankMachinesOnRank(bankMachinesOnRank) +PowerDownManagerStaggered::PowerDownManagerStaggered( + ControllerVector& bankMachinesOnRank, Rank rank) : + bankMachinesOnRank(bankMachinesOnRank) { setUpDummy(powerDownPayload, UINT64_MAX - 1, rank); } @@ -98,7 +98,7 @@ void PowerDownManagerStaggered::evaluate() else if (entryTriggered) { nextCommand = Command::PDEP; - for (auto it : bankMachinesOnRank) + for (auto *it : bankMachinesOnRank) { if (it->isActivated()) { diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index ac061f0c..687655a4 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -49,15 +49,14 @@ class BankMachine; class PowerDownManagerStaggered final : public PowerDownManagerIF { public: - PowerDownManagerStaggered(ControllerVector& bankMachinesOnRank, - Rank rank, CheckerIF& checker); + PowerDownManagerStaggered(ControllerVector& bankMachinesOnRank, Rank rank); void triggerEntry() override; void triggerExit() override; void triggerInterruption() override; CommandTuple::Type getNextCommand() override; - void update(Command) override; + void update(Command command) override; void evaluate() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index b35c9bdf..aeeb67c2 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -47,8 +47,8 @@ namespace DRAMSys RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, ControllerVector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), - memSpec(*config.memSpec), maxPostponed(static_cast(config.refreshMaxPostponed)), + : memSpec(*config.memSpec), bankMachinesOnRank(bankMachinesOnRank), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed)), maxPulledin(-static_cast(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement) { timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(), diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 521e9abe..14776904 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -58,7 +58,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 93b0fbed..18c92d81 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF public: CommandTuple::Type getNextCommand() override; void evaluate() override {} - void update(Command) override {} + void update([[maybe_unused]] Command command) override {} sc_core::sc_time getTimeForNextTrigger() override; private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index fe8151ee..677f888d 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config, ControllerVector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank / 2)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank / 2)) { @@ -128,18 +128,17 @@ void RefreshManagerPer2Bank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalP2B(); return; } - else + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) + if (it->isActivated()) { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } } // TODO: banks should already be blocked for precharge and selection should be skipped @@ -150,54 +149,51 @@ void RefreshManagerPer2Bank::evaluate() skipSelection = true; } return; - } } - else // if (state == RmState::Pulledin) - { - bool allBankPairsBusy = true; + + // if (state == RmState::Pulledin) + bool allBankPairsBusy = true; - currentIterator = remainingBankMachines.begin(); - for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++) + currentIterator = remainingBankMachines.begin(); + for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); + bankIt++) + { + bool pairIsBusy = false; + for (const auto *pairIt : *bankIt) { - bool pairIsBusy = false; - for (const auto* pairIt : *bankIt) + if (!pairIt->isIdle()) { - if (!pairIt->isIdle()) - { - pairIsBusy = true; - break; - } - } - if (!pairIsBusy) - { - allBankPairsBusy = false; - currentIterator = bankIt; + pairIsBusy = true; break; } } - - if (allBankPairsBusy) + if (!pairIsBusy) { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalP2B(); - return; - } - else - { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) - { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } - } - return; + allBankPairsBusy = false; + currentIterator = bankIt; + break; } } + + if (allBankPairsBusy) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalP2B(); + return; + } + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) + { + if (it->isActivated()) + { + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } + } + return; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 26287ae5..79e5b0f9 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 089b5b8e..9185377c 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, ControllerVector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank)) { @@ -109,54 +109,49 @@ void RefreshManagerPerBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalPB(); return; } + + // TODO: bank should already be blocked for precharge and selection should be skipped + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; else { - // TODO: bank should already be blocked for precharge and selection should be skipped - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - { - nextCommand = Command::REFPB; + nextCommand = Command::REFPB; - if (forcedRefresh) - { - (*currentIterator)->block(); - skipSelection = true; - } + if (forcedRefresh) + { + (*currentIterator)->block(); + skipSelection = true; } - return; } + return; } - else // if (state == RmState::Pulledin) + + // if (state == RmState::Pulledin) + bool allBanksBusy = true; + + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { - bool allBanksBusy = true; - - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + if ((*it)->isIdle()) { - if ((*it)->isIdle()) - { - currentIterator = it; - allBanksBusy = false; - break; - } - } - - if (allBanksBusy) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalPB(); - return; - } - else - { - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - nextCommand = Command::REFPB; - - return; + currentIterator = it; + allBanksBusy = false; + break; } } + + if (allBanksBusy) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalPB(); + return; + } + + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; + else + nextCommand = Command::REFPB; + + return; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index 4fde59f2..6d0fe7e0 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index f1cb9013..29721961 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, ControllerVector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerGroup)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerGroup)), refreshManagement(config.refreshManagement) @@ -65,7 +65,7 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, } // allBankMachines: ((0-4-8-12-16-20-24-28), (1-5-9-13-17-21-25-29), ...) - std::list>::iterator it = allBankMachines.begin(); + auto it = allBankMachines.begin(); for (unsigned bankID = 0; bankID < memSpec.banksPerGroup; bankID++) { for (unsigned groupID = 0; groupID < memSpec.groupsPerRank; groupID++) @@ -216,7 +216,7 @@ void RefreshManagerSameBank::evaluate() currentIterator = bankIt; break; } - else if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) + if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) { imtCandidates.emplace_back(bankIt); } @@ -234,7 +234,7 @@ void RefreshManagerSameBank::evaluate() } return; } - else if (!imtCandidates.empty()) + if (!imtCandidates.empty()) { // search for IMT candidates and check if all banks idle bool allGroupsBusy = true; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index 8a5f9c41..04cea387 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -59,7 +59,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index 90d40c52..f6a0f53a 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -48,7 +48,7 @@ namespace DRAMSys class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index 378a007f..dad6725a 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -43,11 +43,19 @@ namespace DRAMSys class RespQueueIF { +protected: + RespQueueIF(const RespQueueIF &) = default; + RespQueueIF(RespQueueIF &&) = default; + RespQueueIF &operator=(const RespQueueIF &) = default; + RespQueueIF &operator=(RespQueueIF &&) = default; + public: - virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0; + RespQueueIF() = default; + virtual ~RespQueueIF() = default; + + virtual void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) = 0; virtual tlm::tlm_generic_payload* nextPayload() = 0; [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; - virtual ~RespQueueIF() = default; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index 9ffa4017..cb698438 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -47,7 +47,7 @@ namespace DRAMSys class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h index fd4a6fbe..02357545 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h @@ -43,8 +43,16 @@ namespace DRAMSys class BufferCounterIF { +protected: + BufferCounterIF(const BufferCounterIF &) = default; + BufferCounterIF(BufferCounterIF &&) = default; + BufferCounterIF &operator=(const BufferCounterIF &) = default; + BufferCounterIF &operator=(BufferCounterIF &&) = default; + public: + BufferCounterIF() = default; virtual ~BufferCounterIF() = default; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(const tlm::tlm_generic_payload& trans) = 0; virtual void removeRequest(const tlm::tlm_generic_payload& trans) = 0; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 046d83ca..43df9e4d 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -77,11 +77,11 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin Bank bank = bankMachine.getBank(); if (!buffer[bank].empty()) return buffer[bank].front(); - else - return nullptr; + + return nullptr; } -bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { if (buffer[bank].size() >= 2) { @@ -92,12 +92,9 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co return false; } -bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFifo::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { - if (buffer[bank].size() >= 2) - return true; - else - return false; + return buffer[bank].size() >= 2; } const std::vector& SchedulerFifo::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index 29c28b2d..813442d8 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF public: explicit SchedulerFifo(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index 93eeb263..dfdd566e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -60,19 +60,19 @@ bool SchedulerFrFcfs::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerFrFcfs::storeRequest(tlm_generic_payload& trans) +void SchedulerFrFcfs::storeRequest(tlm_generic_payload& payload) { - buffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + buffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); } -void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans) +void SchedulerFrFcfs::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + Bank bank = ControllerExtension::getBank(payload); for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - if (*it == &trans) + if (*it == &payload) { buffer[bank].erase(it); break; @@ -89,7 +89,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach { // Search for row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : buffer[bank]) + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -101,10 +101,10 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach return nullptr; } -bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank]) + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == row) { @@ -116,7 +116,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) return false; } -bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return (buffer[bank].size() >= 2); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index 697b46c7..9f0a9178 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF public: explicit SchedulerFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 22c0fdd9..f548f520 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -91,7 +91,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM // Filter all row hits Row openRow = bankMachine.getOpenRow(); std::list rowHits; - for (auto it : buffer[bank]) + for (auto *it : buffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); @@ -126,10 +126,10 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM return nullptr; } -bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank]) + for (auto *it : buffer[bank]) { if (ControllerExtension::getRow(*it) == row) { @@ -141,12 +141,9 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman return false; } -bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { - if (buffer[bank].size() >= 2) - return true; - else - return false; + return buffer[bank].size() >= 2; } const std::vector& SchedulerFrFcfsGrp::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 5101313a..19ed2271 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF public: explicit SchedulerFrFcfsGrp(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 806c554a..0fb5091d 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -63,25 +63,25 @@ bool SchedulerGrpFrFcfs::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& payload) { - if (trans.is_read()) - readBuffer[ControllerExtension::getBank(trans)].push_back(&trans); + if (payload.is_read()) + readBuffer[ControllerExtension::getBank(payload)].push_back(&payload); else - writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); } -void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - lastCommand = trans.get_command(); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + lastCommand = payload.get_command(); + Bank bank = ControllerExtension::getBank(payload); - if (trans.is_read()) - readBuffer[bank].remove(&trans); + if (payload.is_read()) + readBuffer[bank].remove(&payload); else - writeBuffer[bank].remove(&trans); + writeBuffer[bank].remove(&payload); } tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankMachine) const @@ -98,7 +98,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bank]) + for (auto *it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -107,33 +107,13 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No read row hit found or bank precharged return readBuffer[bank].front(); } - else if (!writeBuffer[bank].empty()) - { - if (bankMachine.isActivated()) - { - // Search for write row hit - Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bank]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } - } - // No write row hit found or bank precharged - return writeBuffer[bank].front(); - } - else - return nullptr; - } - else - { if (!writeBuffer[bank].empty()) { if (bankMachine.isActivated()) { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bank]) + for (auto *it : writeBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -142,24 +122,40 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No write row hit found or bank precharged return writeBuffer[bank].front(); } - else if (!readBuffer[bank].empty()) - { - if (bankMachine.isActivated()) - { - // Search for read row hit - Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bank]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } - } - // No read row hit found or bank precharged - return readBuffer[bank].front(); - } - else - return nullptr; + return nullptr; } + + if (!writeBuffer[bank].empty()) + { + if (bankMachine.isActivated()) + { + // Search for write row hit + Row openRow = bankMachine.getOpenRow(); + for (auto *it : writeBuffer[bank]) + { + if (ControllerExtension::getRow(*it) == openRow) + return it; + } + } + // No write row hit found or bank precharged + return writeBuffer[bank].front(); + } + if (!readBuffer[bank].empty()) + { + if (bankMachine.isActivated()) + { + // Search for read row hit + Row openRow = bankMachine.getOpenRow(); + for (auto *it : readBuffer[bank]) + { + if (ControllerExtension::getRow(*it) == openRow) + return it; + } + } + // No read row hit found or bank precharged + return readBuffer[bank].front(); + } + return nullptr; } bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const @@ -168,7 +164,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; if (command == tlm::TLM_READ_COMMAND) { - for (auto it : readBuffer[bank]) + for (auto *it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == row) { @@ -179,37 +175,29 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman } return false; } - else + + for (auto* it : writeBuffer[bank]) { - for (auto it : writeBuffer[bank]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; } - return false; } + + return false; } bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const { if (command == tlm::TLM_READ_COMMAND) { - if (readBuffer[bank].size() >= 2) - return true; - else - return false; - } - else - { - if (writeBuffer[bank].size() >= 2) - return true; - else - return false; + return readBuffer[bank].size() >= 2; } + + return writeBuffer[bank].size() >= 2; + } const std::vector& SchedulerGrpFrFcfs::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index cf14b49e..a39eea78 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF public: explicit SchedulerGrpFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 7673b8fb..1957d020 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -67,25 +67,25 @@ bool SchedulerGrpFrFcfsWm::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& payload) { - if (trans.is_read()) - readBuffer[ControllerExtension::getBank(trans)].push_back(&trans); + if (payload.is_read()) + readBuffer[ControllerExtension::getBank(payload)].push_back(&payload); else - writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); evaluateWriteMode(); } -void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + Bank bank = ControllerExtension::getBank(payload); - if (trans.is_read()) - readBuffer[bank].remove(&trans); + if (payload.is_read()) + readBuffer[bank].remove(&payload); else - writeBuffer[bank].remove(&trans); + writeBuffer[bank].remove(&payload); evaluateWriteMode(); } @@ -102,7 +102,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bank]) + for (auto *it : readBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -111,32 +111,29 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban // No read row hit found or bank precharged return readBuffer[bank].front(); } - else - return nullptr; + return nullptr; } - else + + if (!writeBuffer[bank].empty()) { - if (!writeBuffer[bank].empty()) + if (bankMachine.isActivated()) { - if (bankMachine.isActivated()) + // Search for write row hit + Row openRow = bankMachine.getOpenRow(); + for (auto* it : writeBuffer[bank]) { - // Search for write row hit - Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bank]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } + if (ControllerExtension::getRow(*it) == openRow) + return it; } - // No row hit found or bank precharged - return writeBuffer[bank].front(); } - else - return nullptr; + // No row hit found or bank precharged + return writeBuffer[bank].front(); } + + return nullptr; } -bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm::tlm_command command) const { unsigned rowHitCounter = 0; if (!writeMode) @@ -152,27 +149,28 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command } return false; } - else + + for (auto* it : writeBuffer[bank]) { - for (auto it : writeBuffer[bank]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; } - return false; } + + return false; } -bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm::tlm_command command) const { if (!writeMode) + { return (readBuffer[bank].size() >= 2); - else - return (writeBuffer[bank].size() >= 2); + } + + return (writeBuffer[bank].size() >= 2); } const std::vector& SchedulerGrpFrFcfsWm::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index 85ef3b24..f5c31d31 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF public: explicit SchedulerGrpFrFcfsWm(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index 43012490..0aed1e9e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -47,14 +47,22 @@ class BankMachine; class SchedulerIF { +protected: + SchedulerIF(const SchedulerIF &) = default; + SchedulerIF(SchedulerIF &&) = default; + SchedulerIF &operator=(const SchedulerIF &) = default; + SchedulerIF &operator=(SchedulerIF &&) = default; + public: + SchedulerIF() = default; virtual ~SchedulerIF() = default; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; - virtual void storeRequest(tlm::tlm_generic_payload&) = 0; - virtual void removeRequest(tlm::tlm_generic_payload&) = 0; - [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const = 0; - [[nodiscard]] virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0; - [[nodiscard]] virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0; + virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0; + virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const = 0; + [[nodiscard]] virtual bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0; + [[nodiscard]] virtual bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const = 0; [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index 0571c120..5e5b20d1 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -160,10 +160,9 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { - uint64_t xoredBit; - xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } @@ -205,10 +204,9 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { - uint64_t xoredBit; - xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index 2b02b8ec..41662b4b 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -156,7 +156,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload, +tlm_sync_enum Arbiter::nb_transport_bw([[maybe_unused]] int id, tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + @@ -165,7 +165,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload, return TLM_ACCEPTED; } -void Arbiter::b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) +void Arbiter::b_transport([[maybe_unused]] int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { trans.set_address(trans.get_address() - addressOffset); @@ -173,7 +173,7 @@ void Arbiter::b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time iSocket[static_cast(decodedAddress.channel)]->b_transport(trans, delay); } -unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans) +unsigned int Arbiter::transport_dbg([[maybe_unused]] int id, tlm::tlm_generic_payload& trans) { trans.set_address(trans.get_address() - addressOffset); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index b8bd1183..442cb55d 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,10 +87,10 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& bwDelay); - void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); - unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); + tlm::tlm_sync_enum nb_transport_bw(int id, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); + void b_transport(int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); + unsigned int transport_dbg(int id, tlm::tlm_generic_payload& trans); const sc_core::sc_time tCK; const sc_core::sc_time arbitrationDelayFw; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index d7658cfa..0cd725ad 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -234,9 +234,9 @@ void DRAMSys::bindSockets() } } -void DRAMSys::report(const std::string& message) +void DRAMSys::report(std::string_view message) { - PRINTDEBUGMESSAGE(name(), message); + PRINTDEBUGMESSAGE(name(), message.data()); std::cout << message << std::endl; } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 0df0356b..a641ec9c 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -99,7 +99,7 @@ protected: std::unique_ptr addressDecoder; - void report(const std::string& message); + void report(std::string_view message); void bindSockets(); private: diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index cff46124..8a588d2d 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -56,8 +56,7 @@ public: tlm_utils::simple_target_socket tSocket; SC_CTOR(ReorderBuffer) : - payloadEventQueue(this, &ReorderBuffer::peqCallback), - responseIsPendingInInitator(false) + payloadEventQueue(this, &ReorderBuffer::peqCallback) { iSocket.register_nb_transport_bw(this, &ReorderBuffer::nb_transport_bw); tSocket.register_nb_transport_fw(this, &ReorderBuffer::nb_transport_fw); @@ -68,7 +67,7 @@ private: std::deque pendingRequestsInOrder; std::set receivedResponses; - bool responseIsPendingInInitator; + bool responseIsPendingInInitator = false; // Initiated by dram side @@ -148,8 +147,9 @@ private: { //only send the next response when there response for the oldest pending request (requestsInOrder.front()) //has been received - if (!responseIsPendingInInitator - && receivedResponses.count(pendingRequestsInOrder.front())) { + if (!responseIsPendingInInitator && + (receivedResponses.count(pendingRequestsInOrder.front()) != 0)) + { tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, sc_core::SC_ZERO_TIME); diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index d1c23bfb..46a772cc 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -68,8 +68,8 @@ namespace DRAMSys Dram::Dram(const sc_module_name& name, const Configuration& config) - : sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode), - powerAnalysis(config.powerAnalysis), useMalloc(config.useMalloc) + : sc_module(name), memSpec(*config.memSpec), storeMode(config.storeMode), powerAnalysis(config.powerAnalysis), + useMalloc(config.useMalloc), tSocket("socket") { uint64_t channelSize = memSpec.getSimMemSizeInBytes() / memSpec.numberOfChannels; if (storeMode == Configuration::StoreMode::Store) @@ -77,7 +77,7 @@ Dram::Dram(const sc_module_name& name, const Configuration& config) if (useMalloc) { memory = (unsigned char *)malloc(channelSize); - if (!memory) + if (memory == nullptr) SC_REPORT_FATAL(this->name(), "Memory allocation failed"); } else @@ -261,7 +261,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans) return 0; } -void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay) +void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& delay) { static bool printedWarning = false; diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.h b/src/libdramsys/DRAMSys/simulation/dram/Dram.h index 9227d391..acf16459 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.h @@ -86,6 +86,11 @@ public: tlm_utils::simple_target_socket tSocket; virtual void reportPower(); + + Dram(const Dram &) = delete; + Dram(Dram &&) = delete; + Dram &operator=(const Dram &) = delete; + Dram &operator=(Dram &&) = delete; ~Dram() override; }; diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index f9b982c2..a5ed222c 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -1,3 +1,39 @@ +/* + * Copyright (c) 2022, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + * Derek Christ + */ + #include "Cache.h" #include "MemoryManager.h" @@ -88,33 +124,38 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) fetchLineAndSendEndRequest(trans); return; } - else if (phase == END_REQ) // <--- DRAM side + + if (phase == END_REQ) // <--- DRAM side { lastEndReq = sc_time_stamp(); clearInitiatorBackpressureAndProcessBuffers(); return; } - else if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side + + if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side { // Shortcut, 2 phases in one clearInitiatorBackpressureAndProcessBuffers(); sendEndResponseAndFillLine(trans); return; } - else if (phase == BEGIN_RESP) // <--- DRAM side + + if (phase == BEGIN_RESP) // <--- DRAM side { sendEndResponseAndFillLine(trans); return; } - else if (phase == END_RESP) // core side ---> + + if (phase == END_RESP) // core side ---> { clearTargetBackpressureAndProcessLines(trans); return; } - else if (phase == HIT_HANDLING) // direct hit, account for the hit delay + + if (phase == HIT_HANDLING) // direct hit, account for the hit delay { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); hitQueue.emplace_back(index, tag, &trans); @@ -124,8 +165,8 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) { accessCacheAndSendResponse(trans); - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), @@ -156,8 +197,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) { if (hasBufferSpace()) { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); auto mshrEntry = @@ -196,8 +237,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) // Cache miss and no fetch in progress. // So evict line and allocate empty line. - auto evictedLine = evictLine(index); - if (!evictedLine) + auto *evictedLine = evictLine(index); + if (evictedLine == nullptr) { // Line eviction not possible. endRequestPending = &trans; @@ -280,8 +321,8 @@ bool Cache::isHit(index_t index, tag_t tag) const bool Cache::isHit(uint64_t address) const { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(address); return isHit(index, tag); @@ -340,15 +381,17 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // oldestline is allocated but not yet valid -> fetch in progress return nullptr; } - else if (std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, oldestLine](const Mshr &entry) - { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != mshrQueue.end()) + if (std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [index, oldestLine](const Mshr &entry) { + return (index == entry.index) && (oldestLine.tag == entry.tag); + }) != mshrQueue.end()) { // TODO: solve this in a more clever way // There are still entries in mshrQueue to the oldest line -> do not evict it return nullptr; } - else if (std::find_if(hitQueue.begin(), hitQueue.end(), + if (std::find_if(hitQueue.begin(), hitQueue.end(), [index, oldestLine](const BufferEntry &entry) { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != hitQueue.end()) { @@ -356,29 +399,27 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // There are still hits in hitQueue to the oldest line -> do not evict it return nullptr; } - else + + if (oldestLine.valid && oldestLine.dirty) { - if (oldestLine.valid && oldestLine.dirty) - { - auto &wbTrans = memoryManager.allocate(lineSize); - wbTrans.acquire(); - wbTrans.set_address(encodeAddress(index, oldestLine.tag)); - wbTrans.set_write(); - wbTrans.set_data_length(lineSize); - wbTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); + auto &wbTrans = memoryManager.allocate(lineSize); + wbTrans.acquire(); + wbTrans.set_address(encodeAddress(index, oldestLine.tag)); + wbTrans.set_write(); + wbTrans.set_data_length(lineSize); + wbTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); - if (storageEnabled) - std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans.get_data_ptr()); + if (storageEnabled) + std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans.get_data_ptr()); - writeBuffer.emplace_back(index, oldestLine.tag, &wbTrans); - } - - oldestLine.allocated = false; - oldestLine.valid = false; - oldestLine.dirty = false; - - return &oldestLine; + writeBuffer.emplace_back(index, oldestLine.tag, &wbTrans); } + + oldestLine.allocated = false; + oldestLine.valid = false; + oldestLine.dirty = false; + + return &oldestLine; } /// Align address to cache line size @@ -390,7 +431,7 @@ uint64_t Cache::getAlignedAddress(uint64_t address) const /// Issue read requests for entries in the MshrQueue to the target void Cache::processMshrQueue() { - if (!requestInProgress && !mshrQueue.empty()) + if ((requestInProgress == nullptr) && !mshrQueue.empty()) { // Get the first entry that wasn't already issued to the target auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), [](const Mshr &entry) { return !entry.issued; }); @@ -401,8 +442,8 @@ void Cache::processMshrQueue() // Note: This is the same address for all entries in the requests list uint64_t alignedAddress = getAlignedAddress(mshrIt->requestList.front()->get_address()); - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(alignedAddress); // Search through the writeBuffer in reverse order to get the most recent entry. @@ -469,7 +510,7 @@ void Cache::processMshrQueue() /// Processes writeBuffer (dirty cache line evictions) void Cache::processWriteBuffer() { - if (!requestInProgress && !writeBuffer.empty()) + if ((requestInProgress == nullptr) && !writeBuffer.empty()) { tlm_generic_payload &wbTrans = *writeBuffer.front().trans; @@ -503,8 +544,8 @@ void Cache::processWriteBuffer() /// Fill allocated cache line with data from memory void Cache::fillLine(tlm_generic_payload &trans) { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); CacheLine &allocatedLine = diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h index bd9df4a6..f714bd09 100644 --- a/src/simulator/simulator/Cache.h +++ b/src/simulator/simulator/Cache.h @@ -30,7 +30,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: - * Christian Malek + * Lukas Steiner * Derek Christ */ @@ -205,7 +205,7 @@ private: void fillLine(tlm::tlm_generic_payload &trans); void accessCacheAndSendResponse(tlm::tlm_generic_payload &trans); - void allocateLine(CacheLine *line, tag_t tag); + static void allocateLine(CacheLine *line, tag_t tag); bool isAllocated(index_t index, tag_t tag) const; bool hasBufferSpace() const; diff --git a/src/simulator/simulator/EccModule.cpp b/src/simulator/simulator/EccModule.cpp index cf1a25d0..5933d969 100644 --- a/src/simulator/simulator/EccModule.cpp +++ b/src/simulator/simulator/EccModule.cpp @@ -46,8 +46,8 @@ using namespace tlm; EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder) : sc_core::sc_module(name), payloadEventQueue(this, &EccModule::peqCallback), - addressDecoder(addressDecoder), - memoryManager(false) + memoryManager(false), + addressDecoder(addressDecoder) { iSocket.register_nb_transport_bw(this, &EccModule::nb_transport_bw); tSocket.register_nb_transport_fw(this, &EccModule::nb_transport_fw); @@ -94,12 +94,11 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ // Update the original address to account for the offsets cbPayload.set_address(addressDecoder.encodeAddress(decodedAddress)); - auto currentBlock = alignToBlock(decodedAddress.column); - // In case there is no entry yet. activeEccBlocks.try_emplace(decodedAddress.bank); #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = &cbPayload; @@ -160,8 +159,10 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); - auto currentBlock = alignToBlock(decodedAddress.column); + #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); + if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = pendingRequest; diff --git a/src/simulator/simulator/Initiator.h b/src/simulator/simulator/Initiator.h index 4f6e0187..8cc14675 100644 --- a/src/simulator/simulator/Initiator.h +++ b/src/simulator/simulator/Initiator.h @@ -39,7 +39,14 @@ class Initiator { +protected: + Initiator(const Initiator &) = default; + Initiator(Initiator &&) = default; + Initiator &operator=(const Initiator &) = default; + Initiator &operator=(Initiator &&) = default; + public: + Initiator() = default; virtual ~Initiator() = default; virtual void bind(tlm_utils::multi_target_base<> &target) = 0; diff --git a/src/simulator/simulator/MemoryManager.cpp b/src/simulator/simulator/MemoryManager.cpp index 25c7d480..38f17100 100644 --- a/src/simulator/simulator/MemoryManager.cpp +++ b/src/simulator/simulator/MemoryManager.cpp @@ -41,7 +41,7 @@ using namespace tlm; MemoryManager::MemoryManager(bool storageEnabled) - : numberOfAllocations(0), numberOfFrees(0), storageEnabled(storageEnabled) + : storageEnabled(storageEnabled) {} MemoryManager::~MemoryManager() @@ -82,12 +82,10 @@ tlm_generic_payload& MemoryManager::allocate(unsigned dataLength) return *payload; } - else - { - tlm_generic_payload* result = freePayloads[dataLength].top(); - freePayloads[dataLength].pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads[dataLength].top(); + freePayloads[dataLength].pop(); + return *result; } void MemoryManager::free(tlm_generic_payload* payload) diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index 82c5658c..7cbe33f1 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -32,6 +32,7 @@ * Authors: * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef MEMORYMANAGER_H @@ -45,13 +46,18 @@ class MemoryManager : public tlm::tlm_mm_interface { public: explicit MemoryManager(bool storageEnabled); + MemoryManager(const MemoryManager &) = delete; + MemoryManager(MemoryManager &&) = delete; + MemoryManager &operator=(const MemoryManager &) = delete; + MemoryManager &operator=(MemoryManager &&) = delete; ~MemoryManager() override; + tlm::tlm_generic_payload& allocate(unsigned dataLength); void free(tlm::tlm_generic_payload* payload) override; private: - uint64_t numberOfAllocations; - uint64_t numberOfFrees; + uint64_t numberOfAllocations = 0; + uint64_t numberOfFrees = 0; std::unordered_map> freePayloads; bool storageEnabled = false; }; diff --git a/src/simulator/simulator/Simulator.cpp b/src/simulator/simulator/Simulator.cpp index 823f55c1..dc53fb11 100644 --- a/src/simulator/simulator/Simulator.cpp +++ b/src/simulator/simulator/Simulator.cpp @@ -43,9 +43,9 @@ Simulator::Simulator(DRAMSys::Config::Configuration configuration, std::filesystem::path resourceDirectory) : + memoryManager(configuration.simconfig.StoreMode == DRAMSys::Config::StoreModeType::Store), configuration(std::move(configuration)), - resourceDirectory(std::move(resourceDirectory)), - memoryManager(configuration.simconfig.StoreMode == DRAMSys::Config::StoreModeType::Store) + resourceDirectory(std::move(resourceDirectory)) { if (this->configuration.simconfig.DatabaseRecording.value_or(false)) { diff --git a/src/simulator/simulator/generator/RandomProducer.cpp b/src/simulator/simulator/generator/RandomProducer.cpp index 2d866747..36a3b693 100644 --- a/src/simulator/simulator/generator/RandomProducer.cpp +++ b/src/simulator/simulator/generator/RandomProducer.cpp @@ -47,9 +47,9 @@ RandomProducer::RandomProducer(uint64_t numRequests, : numberOfRequests(numRequests), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), dataLength(dataLength), dataAlignment(dataAlignment), + randomGenerator(this->seed), randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS), maxAddress.value_or((memorySize) - dataLength)) { diff --git a/src/simulator/simulator/generator/SequentialProducer.cpp b/src/simulator/simulator/generator/SequentialProducer.cpp index f2985ef6..2a1aad9c 100644 --- a/src/simulator/simulator/generator/SequentialProducer.cpp +++ b/src/simulator/simulator/generator/SequentialProducer.cpp @@ -50,8 +50,8 @@ SequentialProducer::SequentialProducer(uint64_t numRequests, maxAddress(maxAddress.value_or(memorySize - 1)), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), - dataLength(dataLength) + dataLength(dataLength), + randomGenerator(this->seed) { if (minAddress > memorySize - 1) SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); diff --git a/src/simulator/simulator/generator/TrafficGenerator.cpp b/src/simulator/simulator/generator/TrafficGenerator.cpp index 2a73e82d..b3318040 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.cpp +++ b/src/simulator/simulator/generator/TrafficGenerator.cpp @@ -41,6 +41,8 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator) : + stateTransistions(config.transitions), + generatorPeriod(sc_core::sc_time(1.0 / static_cast(config.clkMhz), sc_core::SC_US)), issuer( config.name.c_str(), memoryManager, @@ -49,9 +51,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine config.maxPendingWriteRequests, [this] { return nextRequest(); }, std::move(transactionFinished), - std::move(terminateInitiator)), - stateTransistions(config.transitions), - generatorPeriod(sc_core::sc_time(1.0 / static_cast(config.clkMhz), sc_core::SC_US)) + std::move(terminateInitiator)) { unsigned int dataLength = config.dataLength.value_or(defaultDataLength); unsigned int dataAlignment = config.dataAlignment.value_or(dataLength); @@ -112,6 +112,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& conf unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator) : + generatorPeriod(sc_core::sc_time(1.0 / static_cast(config.clkMhz), sc_core::SC_US)), issuer( config.name.c_str(), memoryManager, @@ -120,8 +121,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& conf config.maxPendingWriteRequests, [this] { return nextRequest(); }, std::move(transactionFinished), - std::move(terminateInitiator)), - generatorPeriod(sc_core::sc_time(1.0 / static_cast(config.clkMhz), sc_core::SC_US)) + std::move(terminateInitiator)) { unsigned int dataLength = config.dataLength.value_or(defaultDataLength); unsigned int dataAlignment = config.dataAlignment.value_or(dataLength); @@ -163,7 +163,7 @@ Request TrafficGenerator::nextRequest() auto newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; auto idleStateIt = idleStateClks.find(newState.value()); while (idleStateIt != idleStateClks.cend()) @@ -172,7 +172,7 @@ Request TrafficGenerator::nextRequest() newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; currentState = newState.value(); idleStateIt = idleStateClks.find(newState.value()); diff --git a/src/simulator/simulator/hammer/RowHammer.cpp b/src/simulator/simulator/hammer/RowHammer.cpp index feb18d04..c671f151 100644 --- a/src/simulator/simulator/hammer/RowHammer.cpp +++ b/src/simulator/simulator/hammer/RowHammer.cpp @@ -47,7 +47,7 @@ RowHammer::RowHammer(uint64_t numRequests, Request RowHammer::nextRequest() { if (generatedRequests >= numberOfRequests) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; generatedRequests++; diff --git a/src/simulator/simulator/player/StlPlayer.cpp b/src/simulator/simulator/player/StlPlayer.cpp index 2cbcb3b9..9f1e0944 100644 --- a/src/simulator/simulator/player/StlPlayer.cpp +++ b/src/simulator/simulator/player/StlPlayer.cpp @@ -47,15 +47,15 @@ StlPlayer::StlPlayer(std::string_view tracePath, unsigned int defaultDataLength, TraceType traceType, bool storageEnabled) - : traceFile(tracePath.data()), + : traceType(traceType), + storageEnabled(storageEnabled), playerPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), defaultDataLength(defaultDataLength), - traceType(traceType), - storageEnabled(storageEnabled), + traceFile(tracePath.data()), lineBuffers( {std::make_shared>(), std::make_shared>()}), - readoutBuffer(lineBuffers.at(0)), - parseBuffer(lineBuffers.at(1)) + parseBuffer(lineBuffers.at(1)), + readoutBuffer(lineBuffers.at(0)) { readoutBuffer->reserve(LINE_BUFFER_SIZE); parseBuffer->reserve(LINE_BUFFER_SIZE); @@ -93,7 +93,7 @@ Request StlPlayer::nextRequest() parserThread.join(); // The file is read in completely. Nothing more to do. - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; } } diff --git a/src/simulator/simulator/request/Request.h b/src/simulator/simulator/request/Request.h index bc26c785..61eccb0f 100644 --- a/src/simulator/simulator/request/Request.h +++ b/src/simulator/simulator/request/Request.h @@ -46,8 +46,8 @@ struct Request Write, Stop } command; - uint64_t address; - std::size_t length; - sc_core::sc_time delay; - std::vector data; + uint64_t address{}; + std::size_t length{}; + sc_core::sc_time delay{}; + std::vector data{}; }; diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index 19796b7b..fe1a8fa0 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -44,14 +44,14 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name, std::function transactionFinished, std::function terminate) : sc_module(name), + payloadEventQueue(this, &RequestIssuer::peqCallback), memoryManager(memoryManager), clkPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests), - nextRequest(std::move(nextRequest)), transactionFinished(std::move(transactionFinished)), terminate(std::move(terminate)), - payloadEventQueue(this, &RequestIssuer::peqCallback) + nextRequest(std::move(nextRequest)) { SC_THREAD(sendNextRequest); iSocket.register_nb_transport_bw(this, &RequestIssuer::nb_transport_bw); diff --git a/src/simulator/simulator/request/RequestProducer.h b/src/simulator/simulator/request/RequestProducer.h index a7df1935..b41f9ed2 100644 --- a/src/simulator/simulator/request/RequestProducer.h +++ b/src/simulator/simulator/request/RequestProducer.h @@ -39,7 +39,14 @@ class RequestProducer { +protected: + RequestProducer(const RequestProducer &) = default; + RequestProducer(RequestProducer &&) = default; + RequestProducer &operator=(const RequestProducer &) = default; + RequestProducer &operator=(RequestProducer &&) = default; + public: + RequestProducer() = default; virtual ~RequestProducer() = default; virtual Request nextRequest() = 0; diff --git a/src/simulator/simulator/util.cpp b/src/simulator/simulator/util.cpp index 77266721..4ee1de74 100644 --- a/src/simulator/simulator/util.cpp +++ b/src/simulator/simulator/util.cpp @@ -52,21 +52,21 @@ void loadBar(uint64_t x, uint64_t n, unsigned int w, unsigned int granularity) for (unsigned int x = 0; x < c; x++) std::cout << "█"; - if (rest >= 0 && rest < 0.125f && c != w) + if (rest >= 0 && rest < 0.125F && c != w) std::cout << " "; - if (rest >= 0.125f && rest < 2 * 0.125f) + if (rest >= 0.125F && rest < 2 * 0.125F) std::cout << "▏"; - if (rest >= 2 * 0.125f && rest < 3 * 0.125f) + if (rest >= 2 * 0.125F && rest < 3 * 0.125F) std::cout << "▎"; - if (rest >= 3 * 0.125f && rest < 4 * 0.125f) + if (rest >= 3 * 0.125F && rest < 4 * 0.125F) std::cout << "▍"; - if (rest >= 4 * 0.125f && rest < 5 * 0.125f) + if (rest >= 4 * 0.125F && rest < 5 * 0.125F) std::cout << "▌"; - if (rest >= 5 * 0.125f && rest < 6 * 0.125f) + if (rest >= 5 * 0.125F && rest < 6 * 0.125F) std::cout << "▋"; - if (rest >= 6 * 0.125f && rest < 7 * 0.125f) + if (rest >= 6 * 0.125F && rest < 7 * 0.125F) std::cout << "▊"; - if (rest >= 7 * 0.125f && rest < 8 * 0.125f) + if (rest >= 7 * 0.125F && rest < 8 * 0.125F) std::cout << "▉"; for (unsigned int x = c; x < (w - 1); x++) diff --git a/src/util/DRAMSys/util/json.h b/src/util/DRAMSys/util/json.h index 5279c8f1..5d34a4b2 100644 --- a/src/util/DRAMSys/util/json.h +++ b/src/util/DRAMSys/util/json.h @@ -142,6 +142,8 @@ struct adl_serializer> { NLOHMANN_JSON_NAMESPACE_END +// NOLINTBEGIN(cppcoreguidelines-macro-usage) + #define EXTEND_JSON_TO(v1) DRAMSys::util::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); #define EXTEND_JSON_FROM(v1) DRAMSys::util::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); @@ -153,4 +155,6 @@ NLOHMANN_JSON_NAMESPACE_END NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \ } -#endif \ No newline at end of file +// NOLINTEND(cppcoreguidelines-macro-usage) + +#endif // DRAMSYS_UTIL_JSON_H diff --git a/tests/tests_configuration/test_configuration.cpp b/tests/tests_configuration/test_configuration.cpp index 7db7c887..3cdecaf7 100644 --- a/tests/tests_configuration/test_configuration.cpp +++ b/tests/tests_configuration/test_configuration.cpp @@ -87,7 +87,15 @@ protected: PowerDownPolicyType::NoPowerDown, ArbiterType::Simple, 128, - {}}; + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt}; DRAMSys::Config::SimConfig simConfig{0, false, diff --git a/tests/tests_dramsys/AddressDecoderTests.cpp b/tests/tests_dramsys/AddressDecoderTests.cpp index 1c49af9e..29794c50 100644 --- a/tests/tests_dramsys/AddressDecoderTests.cpp +++ b/tests/tests_dramsys/AddressDecoderTests.cpp @@ -47,8 +47,8 @@ protected: addressMappingJson(nlohmann::json::parse(addressMappingJsonString).at("addressmapping")), memSpecJson(nlohmann::json::parse(memSpecJsonString).at("memspec")), addressMappingConfig(addressMappingJson.get()), - memSpec(memSpecConfig), memSpecConfig(memSpecJson.get()), + memSpec(memSpecConfig), addressDecoder(addressMappingConfig, memSpec) { } diff --git a/tests/tests_simulator/cache/TargetMemory.cpp b/tests/tests_simulator/cache/TargetMemory.cpp index adf1af0f..b3f30353 100644 --- a/tests/tests_simulator/cache/TargetMemory.cpp +++ b/tests/tests_simulator/cache/TargetMemory.cpp @@ -49,9 +49,9 @@ TargetMemory::TargetMemory(const sc_core::sc_module_name &name, : sc_core::sc_module(name), tSocket("tSocket"), bufferSize(bufferSize), - peq(this, &TargetMemory::peqCallback), acceptDelay(acceptDelay), - memoryLatency(memoryLatency) + memoryLatency(memoryLatency), + peq(this, &TargetMemory::peqCallback) { tSocket.register_nb_transport_fw(this, &TargetMemory::nb_transport_fw); @@ -155,7 +155,7 @@ void TargetMemory::sendEndRequest(tlm::tlm_generic_payload &trans) bw_phase = tlm::END_REQ; delay = acceptDelay; - tlm::tlm_sync_enum status = tSocket->nb_transport_bw(trans, bw_phase, delay); + tSocket->nb_transport_bw(trans, bw_phase, delay); // Queue internal event to mark beginning of response delay = delay + memoryLatency; // MEMORY Latency diff --git a/tests/tests_simulator/cache/TargetMemory.h b/tests/tests_simulator/cache/TargetMemory.h index 40af3915..ba526a6c 100644 --- a/tests/tests_simulator/cache/TargetMemory.h +++ b/tests/tests_simulator/cache/TargetMemory.h @@ -65,7 +65,7 @@ private: void printBuffer(int max, int n); - static constexpr std::size_t SIZE = static_cast(64 * 1024); + static constexpr std::size_t SIZE = static_cast(64 * 1024); static constexpr std::size_t DEFAULT_BUFFER_SIZE = 8; const std::size_t bufferSize;