From 77decb70ec55dc00c2ce92ea7cd656fc94019655 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 10:53:04 +0200 Subject: [PATCH 01/16] Apply clang-tidy modernize-use-nodiscard fixes --- .../DRAMSys/common/dramExtensions.h | 48 +++++++++---------- src/libdramsys/DRAMSys/common/utils.h | 6 +-- .../DRAMSys/configuration/memspec/MemSpec.h | 28 +++++------ .../configuration/memspec/MemSpecDDR3.h | 6 +-- .../configuration/memspec/MemSpecDDR4.h | 6 +-- .../configuration/memspec/MemSpecGDDR5.h | 8 ++-- .../configuration/memspec/MemSpecGDDR5X.h | 8 ++-- .../configuration/memspec/MemSpecGDDR6.h | 12 ++--- .../configuration/memspec/MemSpecHBM2.h | 10 ++-- .../configuration/memspec/MemSpecLPDDR4.h | 8 ++-- .../configuration/memspec/MemSpecSTTMRAM.h | 4 +- .../configuration/memspec/MemSpecWideIO.h | 6 +-- .../configuration/memspec/MemSpecWideIO2.h | 8 ++-- .../DRAMSys/controller/checker/CheckerDDR3.h | 2 +- .../DRAMSys/controller/checker/CheckerDDR4.h | 2 +- .../DRAMSys/controller/checker/CheckerGDDR5.h | 2 +- .../controller/checker/CheckerGDDR5X.h | 2 +- .../DRAMSys/controller/checker/CheckerGDDR6.h | 2 +- .../DRAMSys/controller/checker/CheckerHBM2.h | 2 +- .../DRAMSys/controller/checker/CheckerIF.h | 2 +- .../controller/checker/CheckerLPDDR4.h | 2 +- .../controller/checker/CheckerSTTMRAM.h | 2 +- .../controller/checker/CheckerWideIO.h | 2 +- .../controller/checker/CheckerWideIO2.h | 2 +- 24 files changed, 90 insertions(+), 90 deletions(-) diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 215785f8..2157bc06 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -50,7 +50,7 @@ class Thread public: explicit Thread(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -64,7 +64,7 @@ class Channel public: explicit Channel(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -78,7 +78,7 @@ class Rank public: explicit Rank(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -92,7 +92,7 @@ class BankGroup public: explicit BankGroup(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -106,12 +106,12 @@ class Bank public: explicit Bank(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } - std::string toString() const + [[nodiscard]] std::string toString() const { return std::to_string(id); } @@ -129,7 +129,7 @@ public: explicit Row(unsigned int id) : id(id), isNoRow(false) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -148,7 +148,7 @@ class Column public: explicit Column(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -166,13 +166,13 @@ public: static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - Thread getThread() const; - Channel getChannel() const; - uint64_t getThreadPayloadID() const; - sc_core::sc_time getTimeOfGeneration() const; + [[nodiscard]] Thread getThread() const; + [[nodiscard]] Channel getChannel() const; + [[nodiscard]] uint64_t getThreadPayloadID() const; + [[nodiscard]] sc_core::sc_time getTimeOfGeneration() const; static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans); static Thread getThread(const tlm::tlm_generic_payload& trans); @@ -199,16 +199,16 @@ public: //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - uint64_t getChannelPayloadID() const; - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getRow() const; - Column getColumn() const; - unsigned getBurstLength() const; + [[nodiscard]] uint64_t getChannelPayloadID() const; + [[nodiscard]] Rank getRank() const; + [[nodiscard]] BankGroup getBankGroup() const; + [[nodiscard]] Bank getBank() const; + [[nodiscard]] Row getRow() const; + [[nodiscard]] Column getColumn() const; + [[nodiscard]] unsigned getBurstLength() const; static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); @@ -264,7 +264,7 @@ private: public: //ChildExtension() = delete; - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; tlm::tlm_generic_payload& getParentTrans(); static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans); @@ -283,7 +283,7 @@ private: public: ParentExtension() = delete; - tlm_extension_base* clone() const override; + [[nodiscard]] tlm_extension_base* clone() const override; void copy_from(const tlm_extension_base& ext) override; static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); const std::vector& getChildTranses(); @@ -294,7 +294,7 @@ public: class EccExtension : public tlm::tlm_extension { public: - tlm_extension_base* clone() const override + [[nodiscard]] tlm_extension_base* clone() const override { return new EccExtension; } diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index 47e3164e..1f3de24b 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -56,9 +56,9 @@ public: TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {} TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {} - sc_core::sc_time getLength() const; - bool timeIsInInterval(const sc_core::sc_time &time) const; - bool intersects(const TimeInterval &other) const; + [[nodiscard]] sc_core::sc_time getLength() const; + [[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const; + [[nodiscard]] bool intersects(const TimeInterval &other) const; }; constexpr const char headline[] = diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index f3189285..83e7afca 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -86,25 +86,25 @@ public: virtual ~MemSpec() = default; - virtual sc_core::sc_time getRefreshIntervalAB() const; - virtual sc_core::sc_time getRefreshIntervalPB() const; - virtual sc_core::sc_time getRefreshIntervalP2B() const; - virtual sc_core::sc_time getRefreshIntervalSB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalSB() const; - virtual unsigned getPer2BankOffset() const; + [[nodiscard]] virtual unsigned getPer2BankOffset() const; - virtual unsigned getRAAIMT() const; - virtual unsigned getRAAMMT() const; - virtual unsigned getRAADEC() const; + [[nodiscard]] virtual unsigned getRAAIMT() const; + [[nodiscard]] virtual unsigned getRAAMMT() const; + [[nodiscard]] virtual unsigned getRAADEC() const; - virtual bool hasRasAndCasBus() const; + [[nodiscard]] virtual bool hasRasAndCasBus() const; - virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - sc_core::sc_time getCommandLength(Command) const; - double getCommandLengthInCycles(Command) const; - uint64_t getSimMemSizeInBytes() const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command) const; + [[nodiscard]] double getCommandLengthInCycles(Command) const; + [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: MemSpec(const DRAMSys::Config::MemSpec& memSpec, diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index a9db6433..f903de1d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -93,10 +93,10 @@ public: const double iDD3P0; const double iDD3P1; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 2849faca..1cf895d8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -100,10 +100,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index b9748814..7b1da4c2 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 8c428d10..87ad3570 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index c45595d9..a216fca8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -91,13 +91,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getRefreshIntervalP2B() const override; - unsigned getPer2BankOffset() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override; + [[nodiscard]] unsigned getPer2BankOffset() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index 2ccba274..b4c681c8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -85,13 +85,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - bool hasRasAndCasBus() const override; + [[nodiscard]] bool hasRasAndCasBus() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 1daa2ab9..30db1f14 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -86,11 +86,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index 7cb862ad..dd2e09d9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -78,8 +78,8 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index d8e0042f..5f62b761 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -98,10 +98,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 8547e640..3b418b62 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -79,11 +79,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h index 6b29108a..357d95bc 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h @@ -49,7 +49,7 @@ class CheckerDDR3 final : public CheckerIF { public: explicit CheckerDDR3(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h index c48aad81..c6762175 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h @@ -51,7 +51,7 @@ class CheckerDDR4 final : public CheckerIF { public: explicit CheckerDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h index 61067704..58de0e38 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h @@ -49,7 +49,7 @@ class CheckerGDDR5 final : public CheckerIF { public: explicit CheckerGDDR5(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h index 482f8e5e..50317f1c 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h @@ -49,7 +49,7 @@ class CheckerGDDR5X final : public CheckerIF { public: explicit CheckerGDDR5X(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h index c86de7f4..fbd4d385 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h @@ -49,7 +49,7 @@ class CheckerGDDR6 final : public CheckerIF { public: explicit CheckerGDDR6(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h index 060e28f4..3da254e1 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h @@ -49,7 +49,7 @@ class CheckerHBM2 final : public CheckerIF { public: explicit CheckerHBM2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index df8bb8b1..35f0ecd4 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -47,7 +47,7 @@ class CheckerIF public: virtual ~CheckerIF() = default; - virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0; }; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h index 2cef3ddd..82203096 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h @@ -49,7 +49,7 @@ class CheckerLPDDR4 final : public CheckerIF { public: explicit CheckerLPDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h index 28d52e2e..f356ba28 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h @@ -49,7 +49,7 @@ class CheckerSTTMRAM final : public CheckerIF { public: explicit CheckerSTTMRAM(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h index c39d1e41..f2f16146 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h @@ -49,7 +49,7 @@ class CheckerWideIO final : public CheckerIF { public: explicit CheckerWideIO(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h index f68f551d..3fca11f7 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h @@ -49,7 +49,7 @@ class CheckerWideIO2 final : public CheckerIF { public: explicit CheckerWideIO2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: From 79a54f11f627432197e9371ba6aa1b5d82e5d44f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 10:56:42 +0200 Subject: [PATCH 02/16] Apply clang-tidy modernize-use-* fixes --- src/libdramsys/DRAMSys/common/DebugManager.cpp | 2 +- src/libdramsys/DRAMSys/common/DebugManager.h | 6 +++--- src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 2 +- src/libdramsys/DRAMSys/common/TlmRecorder.h | 2 +- src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp | 4 ++-- src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h | 2 +- .../DRAMSys/controller/refresh/RefreshManagerSameBank.cpp | 2 +- src/libdramsys/DRAMSys/simulation/ReorderBuffer.h | 5 ++--- src/simulator/simulator/MemoryManager.cpp | 2 +- src/simulator/simulator/MemoryManager.h | 4 ++-- 10 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/libdramsys/DRAMSys/common/DebugManager.cpp b/src/libdramsys/DRAMSys/common/DebugManager.cpp index f558057b..21f06bde 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.cpp +++ b/src/libdramsys/DRAMSys/common/DebugManager.cpp @@ -75,7 +75,7 @@ void DebugManager::openDebugFile(const std::string &filename) } DebugManager::DebugManager() - : debugEnabled(false), writeToConsole(false), writeToFile(false) + { } diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index 411183b2..2d6c0d99 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -73,9 +73,9 @@ public: void openDebugFile(const std::string &filename); private: - bool debugEnabled; - bool writeToConsole; - bool writeToFile; + bool debugEnabled = false; + bool writeToConsole = false; + bool writeToFile = false; std::ofstream debugFile; }; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index 9bbb95c5..4f70fe59 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -53,7 +53,7 @@ namespace DRAMSys { TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) : - name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0), + name(name), config(config), memSpec(*config.memSpec), simulationTimeCoveredByRecording(SC_ZERO_TIME) { currentDataBuffer = &recordingDataBuffer[0]; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 7a950f2e..17bfcbd3 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -162,7 +162,7 @@ private: std::unordered_map currentTransactionsInSystem; - uint64_t totalNumTransactions; + uint64_t totalNumTransactions = 0; sc_core::sc_time simulationTimeCoveredByRecording; sqlite3 *db = nullptr; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index 5c3c140d..b71ae1cd 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -75,8 +75,8 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec, tCK(sc_time(1.0 / fCKMHz, SC_US)), memoryId(memSpec.memoryId), memoryType(memoryType), - burstDuration(tCK* (static_cast(defaultBurstLength) / dataRate)), - memorySizeBytes(0) + burstDuration(tCK* (static_cast(defaultBurstLength) / dataRate)) + { commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); } diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 83e7afca..ff715d1b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -118,7 +118,7 @@ protected: // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; sc_core::sc_time burstDuration; - uint64_t memorySizeBytes; + uint64_t memorySizeBytes = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 08078262..75ecb124 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -65,7 +65,7 @@ RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, } // allBankMachines: ((0-4-8-12-16-20-24-28), (1-5-9-13-17-21-25-29), ...) - std::list>::iterator it = allBankMachines.begin(); + auto it = allBankMachines.begin(); for (unsigned bankID = 0; bankID < memSpec.banksPerGroup; bankID++) { for (unsigned groupID = 0; groupID < memSpec.groupsPerRank; groupID++) diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index cff46124..dac5e389 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -56,8 +56,7 @@ public: tlm_utils::simple_target_socket tSocket; SC_CTOR(ReorderBuffer) : - payloadEventQueue(this, &ReorderBuffer::peqCallback), - responseIsPendingInInitator(false) + payloadEventQueue(this, &ReorderBuffer::peqCallback) { iSocket.register_nb_transport_bw(this, &ReorderBuffer::nb_transport_bw); tSocket.register_nb_transport_fw(this, &ReorderBuffer::nb_transport_fw); @@ -68,7 +67,7 @@ private: std::deque pendingRequestsInOrder; std::set receivedResponses; - bool responseIsPendingInInitator; + bool responseIsPendingInInitator = false; // Initiated by dram side diff --git a/src/simulator/simulator/MemoryManager.cpp b/src/simulator/simulator/MemoryManager.cpp index 25c7d480..9a62e11d 100644 --- a/src/simulator/simulator/MemoryManager.cpp +++ b/src/simulator/simulator/MemoryManager.cpp @@ -41,7 +41,7 @@ using namespace tlm; MemoryManager::MemoryManager(bool storageEnabled) - : numberOfAllocations(0), numberOfFrees(0), storageEnabled(storageEnabled) + : storageEnabled(storageEnabled) {} MemoryManager::~MemoryManager() diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index 82c5658c..f5dc99b5 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -50,8 +50,8 @@ public: void free(tlm::tlm_generic_payload* payload) override; private: - uint64_t numberOfAllocations; - uint64_t numberOfFrees; + uint64_t numberOfAllocations = 0; + uint64_t numberOfFrees = 0; std::unordered_map> freePayloads; bool storageEnabled = false; }; From 8bac84577f4223b874dbdb5345a3dc1b46d43d81 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 10:58:43 +0200 Subject: [PATCH 03/16] Apply clang-tidy modernize-* fixes --- src/libdramsys/DRAMSys/common/DebugManager.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/libdramsys/DRAMSys/common/DebugManager.cpp b/src/libdramsys/DRAMSys/common/DebugManager.cpp index 21f06bde..0bd0de25 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.cpp +++ b/src/libdramsys/DRAMSys/common/DebugManager.cpp @@ -74,10 +74,7 @@ void DebugManager::openDebugFile(const std::string &filename) debugFile.open(filename); } -DebugManager::DebugManager() - -{ -} +DebugManager::DebugManager() = default; DebugManager::~DebugManager() { From 5d8d7c197ef02a606e189955363ce040a900179f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 11:30:55 +0200 Subject: [PATCH 04/16] Apply clang-tidy readability-* fixes --- .../DRAMSys/config/DRAMSysConfiguration.cpp | 3 +- src/libdramsys/DRAMSys/common/DebugManager.h | 1 - src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 2 +- .../DRAMSys/common/dramExtensions.cpp | 11 +--- src/libdramsys/DRAMSys/common/utils.cpp | 6 +- .../DRAMSys/configuration/Configuration.cpp | 24 ++++---- .../DRAMSys/configuration/Configuration.h | 1 - .../configuration/memspec/MemSpecDDR3.cpp | 40 +++++++------ .../configuration/memspec/MemSpecDDR4.cpp | 39 +++++++------ .../configuration/memspec/MemSpecGDDR5.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecGDDR5X.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecGDDR6.cpp | 46 ++++++++------- .../configuration/memspec/MemSpecHBM2.cpp | 36 ++++++------ .../configuration/memspec/MemSpecLPDDR4.cpp | 45 ++++++++------- .../configuration/memspec/MemSpecSTTMRAM.cpp | 36 ++++++------ .../configuration/memspec/MemSpecWideIO.cpp | 39 +++++++------ .../configuration/memspec/MemSpecWideIO2.cpp | 45 ++++++++------- .../DRAMSys/controller/BankMachine.cpp | 56 +++++++------------ .../DRAMSys/controller/Controller.cpp | 14 ++--- .../DRAMSys/controller/ControllerRecordable.h | 3 +- .../controller/cmdmux/CmdMuxOldest.cpp | 6 +- .../controller/cmdmux/CmdMuxStrict.cpp | 6 +- .../powerdown/PowerDownManagerStaggered.cpp | 2 +- .../refresh/RefreshManagerPer2Bank.cpp | 40 ++++++------- .../refresh/RefreshManagerPerBank.cpp | 36 ++++++------ .../refresh/RefreshManagerSameBank.cpp | 4 +- .../controller/scheduler/SchedulerFifo.cpp | 8 +-- .../controller/scheduler/SchedulerFrFcfs.cpp | 4 +- .../scheduler/SchedulerFrFcfsGrp.cpp | 9 +-- .../scheduler/SchedulerGrpFrFcfs.cpp | 36 +++++------- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 29 ++++------ .../DRAMSys/simulation/AddressDecoder.cpp | 4 +- src/libdramsys/DRAMSys/simulation/Arbiter.h | 4 +- .../DRAMSys/simulation/ReorderBuffer.h | 5 +- .../DRAMSys/simulation/dram/Dram.cpp | 2 +- src/simulator/simulator/Cache.cpp | 31 ++++++---- src/simulator/simulator/Cache.h | 2 +- src/simulator/simulator/MemoryManager.cpp | 10 ++-- src/simulator/simulator/util.cpp | 16 +++--- 39 files changed, 392 insertions(+), 401 deletions(-) diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index 8e90dec4..7909bf61 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -124,9 +124,8 @@ Configuration from_path(std::string_view path, std::string_view resourceDirector if (file.is_open()) { json_t simulation = json_t::parse(file, parser_callback, true, true).at(Configuration::KEY); return simulation.get(); - } else { - throw std::runtime_error("Failed to open file " + std::string(path)); } + throw std::runtime_error("Failed to open file " + std::string(path)); } } // namespace DRAMSys::Config diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index 2d6c0d99..cee92445 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -65,7 +65,6 @@ public: DebugManager(const DebugManager&) = delete; DebugManager& operator=(const DebugManager&) = delete; -public: void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); void printDebugMessage(const std::string &sender, const std::string &message); diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index 4f70fe59..b60c14ee 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -78,7 +78,7 @@ TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, c void TlmRecorder::finalize() { - if (db) + if (db != nullptr) closeConnection(); sqlite3_finalize(insertTransactionStatement); sqlite3_finalize(insertRangeStatement); diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.cpp b/src/libdramsys/DRAMSys/common/dramExtensions.cpp index 25b608a1..edbb1fb1 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.cpp +++ b/src/libdramsys/DRAMSys/common/dramExtensions.cpp @@ -403,10 +403,7 @@ void ChildExtension::setExtension(tlm::tlm_generic_payload& childTrans, tlm::tlm bool ChildExtension::isChildTrans(const tlm::tlm_generic_payload& trans) { - if (trans.get_extension() != nullptr) - return true; - else - return false; + return trans.get_extension() != nullptr; } tlm_extension_base* ParentExtension::clone() const @@ -451,10 +448,8 @@ bool ParentExtension::notifyChildTransCompletion() childTranses.clear(); return true; } - else - { - return false; - } + + return false; } bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans) diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index ab919c30..eb00e417 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -60,10 +60,10 @@ bool TimeInterval::intersects(const TimeInterval &other) const sc_time TimeInterval::getLength() const { - if (end > start) - return end - start; - else + if (start > end) return start - end; + + return end - start; } std::string getPhaseName(const tlm_phase &phase) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index 41ea3f69..061b0188 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -71,21 +71,25 @@ enum sc_time_unit string2TimeUnit(const std::string &s) { if (s == "s") return SC_SEC; - else if (s == "ms") + + if (s == "ms") return SC_MS; - else if (s == "us") + + if (s == "us") return SC_US; - else if (s == "ns") + + if (s == "ns") return SC_NS; - else if (s == "ps") + + if (s == "ps") return SC_PS; - else if (s == "fs") + + if (s == "fs") return SC_FS; - else { - SC_REPORT_FATAL("Configuration", - ("Could not convert to enum sc_time_unit: " + s).c_str()); - throw; - } + + SC_REPORT_FATAL("Configuration", + ("Could not convert to enum sc_time_unit: " + s).c_str()); + throw; } void Configuration::loadSimConfig(const DRAMSys::Config::SimConfig &simConfig) diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index 017ef610..5cdfb938 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -59,7 +59,6 @@ public: Configuration(const Configuration&) = delete; Configuration& operator=(const Configuration &) = delete; -public: // MCConfig: enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp, GrpFrFcfs, GrpFrFcfsWm} scheduler = Scheduler::FrFcfs; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 4e9150f4..2c28e968 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -131,37 +131,41 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 10d7a37d..8aff4dde 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -150,37 +150,40 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 9dd86741..c490252d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 2ff265aa..b06fd83a 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -130,44 +130,48 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD; - else - return tRCDWR; + + return tRCDWR; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCPB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 818f251e..d2fb4307 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -143,44 +143,48 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB || command == Command::REFP2B) + + if (command == Command::REFPB || command == Command::REFP2B) return tRFCpb; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 79b8c801..6ab9994d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -131,38 +131,42 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) { if (payload.get_command() == TLM_READ_COMMAND) return tRCDRD + tCK; - else - return tRCDWR + tCK; + + return tRCDWR + tCK; } - else if (command == Command::RD) + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCSB; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; else { diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index a90e67de..35c3dd6f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -136,41 +136,46 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB) return tRPpb + tCK; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab + tCK; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD + 3 * tCK; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration + 3 * tCK; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRTP - 5 * tCK + tRPpb; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + 4 * tCK + burstDuration + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab + tCK; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb + tCK; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK}; - else - { - SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index 76ea4cbd..ef16b158 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -108,35 +108,37 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return tRTP + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; } TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index a72f8d72..b22157ad 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -137,37 +137,40 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo { if (command == Command::PREPB || command == Command::PREAB) return tRP; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tAC + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration + tRP; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration - tCK + tWR + tRP; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFC; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index b1a1a683..f610d8bf 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -121,41 +121,46 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl { if (command == Command::PREPB) return tRPpb; - else if (command == Command::PREAB) + + if (command == Command::PREAB) return tRPab; - else if (command == Command::ACT) + + if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + + if (command == Command::RD) return tRL + tDQSCK + burstDuration; - else if (command == Command::RDA) + + if (command == Command::RDA) return burstDuration - 2 * tCK + tRTP + tRPpb; - else if (command == Command::WR) + + if (command == Command::WR) return tWL + tDQSS + burstDuration; - else if (command == Command::WRA) + + if (command == Command::WRA) return tWL + burstDuration + tCK + tWR + tRPpb; - else if (command == Command::REFAB) + + if (command == Command::REFAB) return tRFCab; - else if (command == Command::REFPB) + + if (command == Command::REFPB) return tRFCpb; - else - { - SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } + + SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + throw; } TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; - else if (command == Command::WR || command == Command::WRA) + + if (command == Command::WR || command == Command::WRA) return {tWL + tDQSS, tWL + tDQSS + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 09b7ceec..3774430c 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -173,16 +173,13 @@ void BankMachineOpen::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -204,7 +201,6 @@ void BankMachineOpen::evaluate() else // row miss nextCommand = Command::PREPB; } - } } } @@ -219,16 +215,13 @@ void BankMachineClosed::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -245,7 +238,6 @@ void BankMachineClosed::evaluate() else nextCommand = Command::WRA; } - } } } @@ -260,16 +252,13 @@ void BankMachineOpenAdaptive::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -303,7 +292,6 @@ void BankMachineOpenAdaptive::evaluate() else // row miss nextCommand = Command::PREPB; } - } } } @@ -319,16 +307,13 @@ void BankMachineClosedAdaptive::evaluate() { tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) - { return; - } - else + + assert(!keepTrans || currentPayload != nullptr); + if (keepTrans) { - assert(!keepTrans || currentPayload != nullptr); - if (keepTrans) - { - if (ControllerExtension::getRow(*newPayload) == openRow) - currentPayload = newPayload; + if (ControllerExtension::getRow(*newPayload) == openRow) + currentPayload = newPayload; } else { @@ -361,7 +346,6 @@ void BankMachineClosedAdaptive::evaluate() else // row miss, can happen when RD/WR mode is switched nextCommand = Command::PREPB; } - } } } diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 9bd58985..b7a5af8c 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -291,7 +291,7 @@ void Controller::controllerMethod() readyCommands.emplace_back(commandTuple); // (4.3) Check for bank commands (PREPB, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rankID]) + for (auto *it : bankMachinesOnRank[rankID]) { commandTuple = it->getNextCommand(); if (std::get(commandTuple) != Command::NOP) @@ -320,7 +320,7 @@ void Controller::controllerMethod() if (command.isRankCommand()) { - for (auto it : bankMachinesOnRank[rank.ID()]) + for (auto *it : bankMachinesOnRank[rank.ID()]) it->update(command); } else if (command.isGroupCommand()) @@ -621,12 +621,10 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate() { return *new tlm_generic_payload(this); } - else - { - tlm_generic_payload* result = freePayloads.top(); - freePayloads.pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads.top(); + freePayloads.pop(); + return *result; } void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans) diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 727cadb6..91fd3832 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -57,7 +57,8 @@ protected: tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; - void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override; + void sendToFrontend(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, + sc_core::sc_time &delay) override; void controllerMethod() override; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index 89487f9d..cd508345 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -73,8 +73,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -179,8 +178,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) return *result; - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index ec288a90..36e5200a 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -83,8 +83,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand nextPayloadID++; return *result; } - else - return {Command::NOP, nullptr, scMaxTime}; + return {Command::NOP, nullptr, scMaxTime}; } @@ -181,8 +180,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC if (std::get(*result).isCasCommand()) nextPayloadID++; return *result; - } - else + } return {Command::NOP, nullptr, scMaxTime}; } diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index e0bad06d..63bbc485 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -98,7 +98,7 @@ void PowerDownManagerStaggered::evaluate() else if (entryTriggered) { nextCommand = Command::PDEP; - for (auto it : bankMachinesOnRank) + for (auto *it : bankMachinesOnRank) { if (it->isActivated()) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index a544c1f6..3ba3a454 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -127,18 +127,17 @@ void RefreshManagerPer2Bank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalP2B(); return; } - else + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) + if (it->isActivated()) { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } } // TODO: banks should already be blocked for precharge and selection should be skipped @@ -149,7 +148,6 @@ void RefreshManagerPer2Bank::evaluate() skipSelection = true; } return; - } } else // if (state == RmState::Pulledin) { @@ -181,21 +179,19 @@ void RefreshManagerPer2Bank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalP2B(); return; } - else + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) { - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto* it : *currentIterator) + if (it->isActivated()) { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } } return; - } } } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 5fb5bac9..3320bcac 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -108,23 +108,21 @@ void RefreshManagerPerBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalPB(); return; } + + // TODO: bank should already be blocked for precharge and selection should be skipped + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; else { - // TODO: bank should already be blocked for precharge and selection should be skipped - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - { - nextCommand = Command::REFPB; + nextCommand = Command::REFPB; - if (forcedRefresh) - { - (*currentIterator)->block(); - skipSelection = true; - } + if (forcedRefresh) + { + (*currentIterator)->block(); + skipSelection = true; + } } return; - } } else // if (state == RmState::Pulledin) { @@ -146,15 +144,13 @@ void RefreshManagerPerBank::evaluate() timeForNextTrigger += memSpec.getRefreshIntervalPB(); return; } - else - { - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - nextCommand = Command::REFPB; - return; - } + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; + else + nextCommand = Command::REFPB; + + return; } } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 75ecb124..802103c0 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -216,7 +216,7 @@ void RefreshManagerSameBank::evaluate() currentIterator = bankIt; break; } - else if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) + if (groupIt->getRefreshManagementCounter() >= memSpec.getRAAIMT()) { imtCandidates.emplace_back(bankIt); } @@ -234,7 +234,7 @@ void RefreshManagerSameBank::evaluate() } return; } - else if (!imtCandidates.empty()) + if (!imtCandidates.empty()) { // search for IMT candidates and check if all banks idle bool allGroupsBusy = true; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 7744ccc4..10df01b8 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -77,8 +77,7 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin unsigned bankID = bankMachine.getBank().ID(); if (!buffer[bankID].empty()) return buffer[bankID].front(); - else - return nullptr; + return nullptr; } bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const @@ -94,10 +93,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const { - if (buffer[bank.ID()].size() >= 2) - return true; - else - return false; + return buffer[bank.ID()].size() >= 2; } const std::vector& SchedulerFifo::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index 8298d362..f71f0f68 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -89,7 +89,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach { // Search for row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : buffer[bankID]) + for (auto *it : buffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -104,7 +104,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank.ID()]) + for (auto *it : buffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 0cd7dc3b..6017dc28 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -91,7 +91,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM // Filter all row hits Row openRow = bankMachine.getOpenRow(); std::list rowHits; - for (auto it : buffer[bankID]) + for (auto *it : buffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) rowHits.push_back(it); @@ -129,7 +129,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank.ID()]) + for (auto *it : buffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -143,10 +143,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const { - if (buffer[bank.ID()].size() >= 2) - return true; - else - return false; + return buffer[bank.ID()].size() >= 2; } const std::vector& SchedulerFrFcfsGrp::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 0d9075c9..560470e2 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -98,7 +98,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bankID]) + for (auto *it : readBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -107,7 +107,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No read row hit found or bank precharged return readBuffer[bankID].front(); } - else if (!writeBuffer[bankID].empty()) + if (!writeBuffer[bankID].empty()) { if (bankMachine.isActivated()) { @@ -133,7 +133,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bankID]) + for (auto *it : writeBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -142,7 +142,7 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No write row hit found or bank precharged return writeBuffer[bankID].front(); } - else if (!readBuffer[bankID].empty()) + if (!readBuffer[bankID].empty()) { if (bankMachine.isActivated()) { @@ -168,7 +168,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman unsigned rowHitCounter = 0; if (command == tlm::TLM_READ_COMMAND) { - for (auto it : readBuffer[bank.ID()]) + for (auto *it : readBuffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -179,36 +179,28 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman } return false; } - else + + for (auto it : writeBuffer[bank.ID()]) { - for (auto it : writeBuffer[bank.ID()]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } } return false; - } } bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const { if (command == tlm::TLM_READ_COMMAND) { - if (readBuffer[bank.ID()].size() >= 2) - return true; - else - return false; + return readBuffer[bank.ID()].size() >= 2; } else { - if (writeBuffer[bank.ID()].size() >= 2) - return true; - else - return false; + return writeBuffer[bank.ID()].size() >= 2; } } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index f6f2c95c..eb207104 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -102,7 +102,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for read row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bankID]) + for (auto *it : readBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -111,8 +111,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban // No read row hit found or bank precharged return readBuffer[bankID].front(); } - else - return nullptr; + return nullptr; } else { @@ -122,7 +121,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bankID]) + for (auto *it : writeBuffer[bankID]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -131,8 +130,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban // No row hit found or bank precharged return writeBuffer[bankID].front(); } - else - return nullptr; + return nullptr; } } @@ -152,27 +150,24 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command } return false; } - else + + for (auto it : writeBuffer[bank.ID()]) { - for (auto it : writeBuffer[bank.ID()]) + if (ControllerExtension::getRow(*it) == row) { - if (ControllerExtension::getRow(*it) == row) - { - rowHitCounter++; - if (rowHitCounter == 2) - return true; - } + rowHitCounter++; + if (rowHitCounter == 2) + return true; + } } return false; - } } bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const { if (!writeMode) return (readBuffer[bank.ID()].size() >= 2); - else - return (writeBuffer[bank.ID()].size() >= 2); + return (writeBuffer[bank.ID()].size() >= 2); } const std::vector& SchedulerGrpFrFcfsWm::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index 0571c120..fed6a3c8 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -160,7 +160,7 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); @@ -205,7 +205,7 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto& it : vXor) + for (const auto &it : vXor) { uint64_t xoredBit; xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index 70e69c0d..2de50c7b 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,8 +87,8 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload& trans, - tlm::tlm_phase& phase, sc_core::sc_time& bwDelay); + tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index dac5e389..8a588d2d 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -147,8 +147,9 @@ private: { //only send the next response when there response for the oldest pending request (requestsInOrder.front()) //has been received - if (!responseIsPendingInInitator - && receivedResponses.count(pendingRequestsInOrder.front())) { + if (!responseIsPendingInInitator && + (receivedResponses.count(pendingRequestsInOrder.front()) != 0)) + { tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front(); responseIsPendingInInitator = true; sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, sc_core::SC_ZERO_TIME); diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index ff65b291..c0a988eb 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -77,7 +77,7 @@ Dram::Dram(const sc_module_name& name, const Configuration& config) if (useMalloc) { memory = (unsigned char *)malloc(channelSize); - if (!memory) + if (memory == nullptr) SC_REPORT_FATAL(this->name(), "Memory allocation failed"); } else diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index 06739cfe..9aaf98ae 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -93,30 +93,35 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) fetchLineAndSendEndRequest(trans); return; } - else if (phase == END_REQ) // <--- DRAM side + + if (phase == END_REQ) // <--- DRAM side { lastEndReq = sc_time_stamp(); clearInitiatorBackpressureAndProcessBuffers(); return; } - else if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side + + if (phase == BEGIN_RESP && &trans == requestInProgress) // <--- DRAM side { // Shortcut, 2 phases in one clearInitiatorBackpressureAndProcessBuffers(); sendEndResponseAndFillLine(trans); return; } - else if (phase == BEGIN_RESP) // <--- DRAM side + + if (phase == BEGIN_RESP) // <--- DRAM side { sendEndResponseAndFillLine(trans); return; } - else if (phase == END_RESP) // core side ---> + + if (phase == END_RESP) // core side ---> { clearTargetBackpressureAndProcessLines(trans); return; } - else if (phase == HIT_HANDLING) // direct hit, account for the hit delay + + if (phase == HIT_HANDLING) // direct hit, account for the hit delay { index_t index; tag_t tag; @@ -201,8 +206,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) // Cache miss and no fetch in progress. // So evict line and allocate empty line. - auto evictedLine = evictLine(index); - if (!evictedLine) + auto *evictedLine = evictLine(index); + if (evictedLine == nullptr) { // Line eviction not possible. endRequestPending = &trans; @@ -345,9 +350,11 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // oldestline is allocated but not yet valid -> fetch in progress return nullptr; } - else if (std::find_if(mshrQueue.begin(), mshrQueue.end(), - [index, oldestLine](const Mshr &entry) - { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != mshrQueue.end()) + if (std::find_if(mshrQueue.begin(), + mshrQueue.end(), + [index, oldestLine](const Mshr &entry) { + return (index == entry.index) && (oldestLine.tag == entry.tag); + }) != mshrQueue.end()) { // TODO: solve this in a more clever way // There are still entries in mshrQueue to the oldest line -> do not evict it @@ -395,7 +402,7 @@ uint64_t Cache::getAlignedAddress(uint64_t address) const /// Issue read requests for entries in the MshrQueue to the target void Cache::processMshrQueue() { - if (!requestInProgress && !mshrQueue.empty()) + if ((requestInProgress == nullptr) && !mshrQueue.empty()) { // Get the first entry that wasn't already issued to the target auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), [](const Mshr &entry) { return !entry.issued; }); @@ -474,7 +481,7 @@ void Cache::processMshrQueue() /// Processes writeBuffer (dirty cache line evictions) void Cache::processWriteBuffer() { - if (!requestInProgress && !writeBuffer.empty()) + if ((requestInProgress == nullptr) && !writeBuffer.empty()) { tlm_generic_payload &wbTrans = *writeBuffer.front().trans; diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h index dc9ff74e..3236d54f 100644 --- a/src/simulator/simulator/Cache.h +++ b/src/simulator/simulator/Cache.h @@ -204,7 +204,7 @@ private: void fillLine(tlm::tlm_generic_payload &trans); void accessCacheAndSendResponse(tlm::tlm_generic_payload &trans); - void allocateLine(CacheLine *line, tag_t tag); + static void allocateLine(CacheLine *line, tag_t tag); bool isAllocated(index_t index, tag_t tag) const; bool hasBufferSpace() const; diff --git a/src/simulator/simulator/MemoryManager.cpp b/src/simulator/simulator/MemoryManager.cpp index 9a62e11d..38f17100 100644 --- a/src/simulator/simulator/MemoryManager.cpp +++ b/src/simulator/simulator/MemoryManager.cpp @@ -82,12 +82,10 @@ tlm_generic_payload& MemoryManager::allocate(unsigned dataLength) return *payload; } - else - { - tlm_generic_payload* result = freePayloads[dataLength].top(); - freePayloads[dataLength].pop(); - return *result; - } + + tlm_generic_payload *result = freePayloads[dataLength].top(); + freePayloads[dataLength].pop(); + return *result; } void MemoryManager::free(tlm_generic_payload* payload) diff --git a/src/simulator/simulator/util.cpp b/src/simulator/simulator/util.cpp index 77266721..4ee1de74 100644 --- a/src/simulator/simulator/util.cpp +++ b/src/simulator/simulator/util.cpp @@ -52,21 +52,21 @@ void loadBar(uint64_t x, uint64_t n, unsigned int w, unsigned int granularity) for (unsigned int x = 0; x < c; x++) std::cout << "█"; - if (rest >= 0 && rest < 0.125f && c != w) + if (rest >= 0 && rest < 0.125F && c != w) std::cout << " "; - if (rest >= 0.125f && rest < 2 * 0.125f) + if (rest >= 0.125F && rest < 2 * 0.125F) std::cout << "▏"; - if (rest >= 2 * 0.125f && rest < 3 * 0.125f) + if (rest >= 2 * 0.125F && rest < 3 * 0.125F) std::cout << "▎"; - if (rest >= 3 * 0.125f && rest < 4 * 0.125f) + if (rest >= 3 * 0.125F && rest < 4 * 0.125F) std::cout << "▍"; - if (rest >= 4 * 0.125f && rest < 5 * 0.125f) + if (rest >= 4 * 0.125F && rest < 5 * 0.125F) std::cout << "▌"; - if (rest >= 5 * 0.125f && rest < 6 * 0.125f) + if (rest >= 5 * 0.125F && rest < 6 * 0.125F) std::cout << "▋"; - if (rest >= 6 * 0.125f && rest < 7 * 0.125f) + if (rest >= 6 * 0.125F && rest < 7 * 0.125F) std::cout << "▊"; - if (rest >= 7 * 0.125f && rest < 8 * 0.125f) + if (rest >= 7 * 0.125F && rest < 8 * 0.125F) std::cout << "▉"; for (unsigned int x = c; x < (w - 1); x++) From 2d590fda0da0b8b0bca1c13cf96bb23023ee6f7a Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 11:52:00 +0200 Subject: [PATCH 05/16] Apply clang-tidy readability-named-parameter fixes --- src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecDDR3.cpp | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecDDR4.cpp | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecGDDR5.cpp | 2 +- .../DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp | 2 +- .../DRAMSys/configuration/memspec/MemSpecGDDR6.cpp | 2 +- .../DRAMSys/configuration/memspec/MemSpecHBM2.cpp | 2 +- .../DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecWideIO.cpp | 4 ++-- .../DRAMSys/configuration/memspec/MemSpecWideIO2.cpp | 4 ++-- src/libdramsys/DRAMSys/controller/BankMachine.h | 2 +- src/libdramsys/DRAMSys/controller/Command.h | 2 +- src/libdramsys/DRAMSys/controller/Controller.cpp | 2 +- .../DRAMSys/controller/ControllerRecordable.cpp | 4 ++-- src/libdramsys/DRAMSys/controller/ManagerIF.h | 2 +- src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h | 2 +- .../DRAMSys/controller/cmdmux/CmdMuxOldest.h | 4 ++-- .../DRAMSys/controller/cmdmux/CmdMuxStrict.h | 4 ++-- .../controller/powerdown/PowerDownManagerDummy.h | 2 +- .../controller/powerdown/PowerDownManagerStaggered.h | 2 +- .../DRAMSys/controller/refresh/RefreshManagerAllBank.h | 2 +- .../DRAMSys/controller/refresh/RefreshManagerDummy.h | 2 +- .../controller/refresh/RefreshManagerPer2Bank.h | 2 +- .../DRAMSys/controller/refresh/RefreshManagerPerBank.h | 2 +- .../controller/refresh/RefreshManagerSameBank.h | 2 +- .../DRAMSys/controller/respqueue/RespQueueFifo.h | 2 +- .../DRAMSys/controller/respqueue/RespQueueIF.h | 2 +- .../DRAMSys/controller/respqueue/RespQueueReorder.h | 2 +- .../DRAMSys/controller/scheduler/SchedulerFifo.h | 10 +++++----- .../DRAMSys/controller/scheduler/SchedulerFrFcfs.h | 10 +++++----- .../DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h | 10 +++++----- .../DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h | 10 +++++----- .../controller/scheduler/SchedulerGrpFrFcfsWm.h | 10 +++++----- .../DRAMSys/controller/scheduler/SchedulerIF.h | 10 +++++----- src/libdramsys/DRAMSys/simulation/Arbiter.cpp | 4 ++-- src/libdramsys/DRAMSys/simulation/Arbiter.h | 4 ++-- 37 files changed, 73 insertions(+), 73 deletions(-) diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index ff715d1b..75979552 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -102,8 +102,8 @@ public: [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - [[nodiscard]] sc_core::sc_time getCommandLength(Command) const; - [[nodiscard]] double getCommandLengthInCycles(Command) const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command /*command*/) const; + [[nodiscard]] double getCommandLengthInCycles(Command /*command*/) const; [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 2c28e968..a46cb218 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -127,7 +127,7 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -156,7 +156,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 8aff4dde..8e86697b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -146,7 +146,7 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -174,7 +174,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index c490252d..62c38281 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index b06fd83a..88fac485 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index d2fb4307..94fb972b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -175,7 +175,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 6ab9994d..cb028a52 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -162,7 +162,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index 35c3dd6f..a1b1fe1f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB) return tRPpb + tCK; @@ -166,7 +166,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index ef16b158..e2d7aa2d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -104,7 +104,7 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -129,7 +129,7 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl return SC_ZERO_TIME; } -TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const +TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index b22157ad..f78bd97e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -133,7 +133,7 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -161,7 +161,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index f610d8bf..fd193b81 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::PREPB) return tRPpb; @@ -151,7 +151,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl throw; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index d646555f..39a04f2b 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -53,7 +53,7 @@ class BankMachine : public ManagerIF { public: CommandTuple::Type getNextCommand() override; - void update(Command) override; + void update(Command /*command*/) override; void block(); [[nodiscard]] Rank getRank() const; diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 4b28e8b4..4e43523d 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -84,7 +84,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 26 DECLARE_EXTENDED_PHASE(END_SREF); // 27 #ifdef DRAMPOWER -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase /*phase*/ /*phase*/); #endif bool phaseHasDataStrobe(tlm::tlm_phase phase); diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index b7a5af8c..dbc0f7c3 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -440,7 +440,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&) +tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& /*trans*/,tlm_phase& /*phase*/, sc_time& /*delay*/) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index 056ab541..16f86af0 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -65,8 +65,8 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload&, - tlm_phase&, sc_time&) +tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload& /*trans*/, + tlm_phase& /*phase*/, sc_time& /*delay*/) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 65b4c4db..99e95da6 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -45,7 +45,7 @@ class ManagerIF public: virtual void evaluate() = 0; virtual CommandTuple::Type getNextCommand() = 0; - virtual void update(Command) = 0; + virtual void update(Command /*command*/) = 0; virtual ~ManagerIF() = default; }; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index 8f02c1bc..996295e5 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -44,7 +44,7 @@ class CmdMuxIF { public: virtual ~CmdMuxIF() = default; - virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0; + virtual CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index e8a24502..c52ffdf0 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF { public: explicit CmdMuxOldest(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; private: const MemSpec& memSpec; @@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF { public: explicit CmdMuxOldestRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; private: const MemSpec& memSpec; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index b69f1aa7..eb1b5b4a 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF { public: explicit CmdMuxStrict(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; private: uint64_t nextPayloadID = 1; @@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: explicit CmdMuxStrictRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands &) override; + CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; private: uint64_t nextPayloadID = 1; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index 07604fb4..f874a198 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -50,7 +50,7 @@ public: void triggerInterruption() override {} CommandTuple::Type getNextCommand() override; - void update(Command) override {} + void update(Command /*command*/) override {} void evaluate() override {} }; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index d0aff5f9..5b9175d9 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -57,7 +57,7 @@ public: void triggerInterruption() override; CommandTuple::Type getNextCommand() override; - void update(Command) override; + void update(Command /*command*/) override; void evaluate() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index abd9a8be..7ccd7ecd 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -58,7 +58,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command /*command*/) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 93b0fbed..72328a5e 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF public: CommandTuple::Type getNextCommand() override; void evaluate() override {} - void update(Command) override {} + void update(Command /*command*/) override {} sc_core::sc_time getTimeForNextTrigger() override; private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 37f505ba..88e7a489 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command /*command*/) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index e1ba8f42..294b9412 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command /*command*/) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index 632572b1..28b7d01d 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -59,7 +59,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command) override; + void update(Command /*command*/) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index 90d40c52..cce032be 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -48,7 +48,7 @@ namespace DRAMSys class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index 378a007f..ec95ee23 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -44,7 +44,7 @@ namespace DRAMSys class RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) = 0; + virtual void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) = 0; virtual tlm::tlm_generic_payload* nextPayload() = 0; [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; virtual ~RespQueueIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index 9ffa4017..4a355b17 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -47,7 +47,7 @@ namespace DRAMSys class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload*, sc_core::sc_time) override; + void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index bbeb3089..9bcb672d 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF public: explicit SchedulerFifo(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; + void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; + [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index a91531ec..e317b044 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF public: explicit SchedulerFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; + void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; + [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 717a6c5a..1f0536d7 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF public: explicit SchedulerFrFcfsGrp(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; + void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; + [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index 904064a9..77e7e7ba 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF public: explicit SchedulerGrpFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; + void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; + [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index d7ef4fed..fb4b2c2d 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF public: explicit SchedulerGrpFrFcfsWm(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload&) override; - void removeRequest(tlm::tlm_generic_payload&) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const override; - [[nodiscard]] bool hasFurtherRequest(Bank, tlm::tlm_command) const override; + void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; + void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; + [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index 43012490..f7b2577c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -50,11 +50,11 @@ class SchedulerIF public: virtual ~SchedulerIF() = default; [[nodiscard]] virtual bool hasBufferSpace() const = 0; - virtual void storeRequest(tlm::tlm_generic_payload&) = 0; - virtual void removeRequest(tlm::tlm_generic_payload&) = 0; - [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine&) const = 0; - [[nodiscard]] virtual bool hasFurtherRowHit(Bank, Row, tlm::tlm_command) const = 0; - [[nodiscard]] virtual bool hasFurtherRequest(Bank, tlm::tlm_command) const = 0; + virtual void storeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; + virtual void removeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const = 0; + [[nodiscard]] virtual bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const = 0; + [[nodiscard]] virtual bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const = 0; [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index d7a6c383..6517e8fa 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -156,7 +156,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload, +tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + @@ -165,7 +165,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload, return TLM_ACCEPTED; } -void Arbiter::b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) +void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { trans.set_address(trans.get_address() - addressOffset); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index 2de50c7b..bc90e2c1 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,9 +87,9 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload &payload, + tlm::tlm_sync_enum nb_transport_bw(int /*id*/, tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); - void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); + void b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); const sc_core::sc_time tCK; From ad96e3ba1444436f8a874a7f23fd3b88ba3c48b3 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 13:08:26 +0200 Subject: [PATCH 06/16] Apply default clang-tidy fixes --- src/configuration/DRAMSys/config/TraceSetup.h | 22 +++--- src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 21 ++--- .../DRAMSys/common/dramExtensions.h | 2 +- .../configuration/memspec/MemSpecHBM2.cpp | 10 +-- .../controller/checker/CheckerDDR3.cpp | 4 +- .../controller/checker/CheckerDDR4.cpp | 4 +- .../controller/checker/CheckerGDDR5.cpp | 4 +- .../controller/checker/CheckerGDDR5X.cpp | 4 +- .../controller/checker/CheckerGDDR6.cpp | 4 +- .../controller/checker/CheckerHBM2.cpp | 4 +- .../controller/checker/CheckerLPDDR4.cpp | 4 +- .../controller/checker/CheckerSTTMRAM.cpp | 4 +- .../controller/checker/CheckerWideIO.cpp | 4 +- .../controller/checker/CheckerWideIO2.cpp | 4 +- .../controller/cmdmux/CmdMuxOldest.cpp | 4 +- .../controller/cmdmux/CmdMuxStrict.cpp | 4 +- .../refresh/RefreshManagerPer2Bank.cpp | 70 ++++++++-------- .../refresh/RefreshManagerPerBank.cpp | 55 +++++++------ .../scheduler/SchedulerGrpFrFcfs.cpp | 79 +++++++++---------- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 30 ++++--- .../DRAMSys/simulation/AddressDecoder.cpp | 6 +- src/simulator/simulator/Cache.cpp | 26 +++--- src/simulator/simulator/request/Request.h | 4 +- 23 files changed, 183 insertions(+), 190 deletions(-) diff --git a/src/configuration/DRAMSys/config/TraceSetup.h b/src/configuration/DRAMSys/config/TraceSetup.h index 8f3e4fb4..8a4d9aa3 100644 --- a/src/configuration/DRAMSys/config/TraceSetup.h +++ b/src/configuration/DRAMSys/config/TraceSetup.h @@ -70,7 +70,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution, {{AddressDistribution::Invalid struct TracePlayer { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -81,10 +81,10 @@ NLOHMANN_JSONIFY_ALL_THINGS( struct TrafficGeneratorActiveState { - unsigned int id; + unsigned int id{}; - uint64_t numRequests; - double rwRatio; + uint64_t numRequests{}; + double rwRatio{}; AddressDistribution addressDistribution; std::optional addressIncrement; std::optional minAddress; @@ -120,7 +120,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probabili struct TrafficGenerator { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -130,8 +130,8 @@ struct TrafficGenerator std::optional dataLength; std::optional dataAlignment; - uint64_t numRequests; - double rwRatio; + uint64_t numRequests{}; + double rwRatio{}; AddressDistribution addressDistribution; std::optional addressIncrement; std::optional minAddress; @@ -156,7 +156,7 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator, struct TrafficGeneratorStateMachine { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; @@ -183,13 +183,13 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine, struct RowHammer { - uint64_t clkMhz; + uint64_t clkMhz{}; std::string name; std::optional maxPendingReadRequests; std::optional maxPendingWriteRequests; - uint64_t numRequests; - uint64_t rowIncrement; + uint64_t numRequests{}; + uint64_t rowIncrement{}; }; NLOHMANN_JSONIFY_ALL_THINGS( diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index b60c14ee..d2dbfe9a 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -52,18 +52,21 @@ using namespace tlm; namespace DRAMSys { -TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) : - name(name), config(config), memSpec(*config.memSpec), - simulationTimeCoveredByRecording(SC_ZERO_TIME) +TlmRecorder::TlmRecorder(const std::string &name, + const Configuration &config, + const std::string &dbName) : + name(name), + config(config), + memSpec(*config.memSpec), + currentDataBuffer(&recordingDataBuffer.at(0)), + storageDataBuffer(&recordingDataBuffer.at(1)), + simulationTimeCoveredByRecording(SC_ZERO_TIME) { - currentDataBuffer = &recordingDataBuffer[0]; - storageDataBuffer = &recordingDataBuffer[1]; - currentDataBuffer->reserve(transactionCommitRate); storageDataBuffer->reserve(transactionCommitRate); openDB(dbName); - char *sErrMsg; + char *sErrMsg = nullptr; sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.cache_size=10000", nullptr, nullptr, &sErrMsg); sqlite3_exec(db, "PRAGMA main.locking_mode=EXCLUSIVE", nullptr, nullptr, &sErrMsg); @@ -146,7 +149,7 @@ void TlmRecorder::recordPhase(tlm_generic_payload& trans, const tlm_phase& phase } else if (isFixedCommandPhase(phase)) { - tlm_generic_payload* keyTrans; + tlm_generic_payload* keyTrans = nullptr; if (ChildExtension::isChildTrans(trans)) { keyTrans = &ChildExtension::getParentTrans(trans); @@ -210,7 +213,7 @@ void TlmRecorder::introduceTransactionToSystem(tlm_generic_payload& trans) { totalNumTransactions++; - char commandChar; + char commandChar = 0; tlm_command command = trans.get_command(); if (command == TLM_READ_COMMAND) commandChar = 'R'; diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 2157bc06..34c479da 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -301,7 +301,7 @@ public: void copy_from(tlm_extension_base const &ext) override { - auto const &cpyFrom = static_cast(ext); + auto const &cpyFrom = dynamic_cast(ext); } }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index cb028a52..431ae424 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -139,6 +139,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload return tRCDWR + tCK; } + if (command == Command::RD) return tRL + tDQSCK + burstDuration; @@ -166,13 +167,12 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; + if (command == Command::WR || command == Command::WRA) return {tWL, tWL + burstDuration}; - else - { - SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); - return {}; - } + + SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp index 497f3bf3..1c31bbc9 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerDDR3::CheckerDDR3(const Configuration& config) +CheckerDDR3::CheckerDDR3(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp index 10615c83..7ed7cb27 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerDDR4::CheckerDDR4(const Configuration& config) +CheckerDDR4::CheckerDDR4(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp index f8320909..8b10e2f2 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR5::CheckerGDDR5(const Configuration& config) +CheckerGDDR5::CheckerGDDR5(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp index 682a2196..f7a96044 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) +CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp index 7b90405e..70332aac 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerGDDR6::CheckerGDDR6(const Configuration& config) +CheckerGDDR6::CheckerGDDR6(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp index 1e645b74..2ac82fb5 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerHBM2::CheckerHBM2(const Configuration& config) +CheckerHBM2::CheckerHBM2(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index f71b6502..6cf54390 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) +CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp index ab2833c6..feb9f850 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) +CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp index 25a91656..1604e724 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerWideIO::CheckerWideIO(const Configuration& config) +CheckerWideIO::CheckerWideIO(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp index ebc6e967..9a2c57a4 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp @@ -44,9 +44,9 @@ using namespace tlm; namespace DRAMSys { -CheckerWideIO2::CheckerWideIO2(const Configuration& config) +CheckerWideIO2::CheckerWideIO2(const Configuration& config) : + memSpec(dynamic_cast(config.memSpec.get())) { - memSpec = dynamic_cast(config.memSpec.get()); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index cd508345..830e049f 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand { auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -102,7 +102,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC auto resultCas = readyCasCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index 36e5200a..15627c42 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -47,7 +47,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand { auto result = readyCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; @@ -112,7 +112,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC auto resultCas = readyCasCommands.cend(); uint64_t lastPayloadID = UINT64_MAX; - uint64_t newPayloadID; + uint64_t newPayloadID = 0; sc_time lastTimestamp = scMaxTime; sc_time newTimestamp; diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index 3ba3a454..e1a90770 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -149,50 +149,50 @@ void RefreshManagerPer2Bank::evaluate() } return; } - else // if (state == RmState::Pulledin) + + // if (state == RmState::Pulledin) + bool allBankPairsBusy = true; + + currentIterator = remainingBankMachines.begin(); + for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); + bankIt++) { - bool allBankPairsBusy = true; - - currentIterator = remainingBankMachines.begin(); - for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++) + bool pairIsBusy = false; + for (const auto *pairIt : *bankIt) { - bool pairIsBusy = false; - for (const auto* pairIt : *bankIt) + if (!pairIt->isIdle()) { - if (!pairIt->isIdle()) - { - pairIsBusy = true; - break; - } - } - if (!pairIsBusy) - { - allBankPairsBusy = false; - currentIterator = bankIt; + pairIsBusy = true; break; } } - - if (allBankPairsBusy) + if (!pairIsBusy) { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalP2B(); - return; + allBankPairsBusy = false; + currentIterator = bankIt; + break; } - - nextCommand = Command::REFP2B; - currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); - for (auto *it : *currentIterator) - { - if (it->isActivated()) - { - nextCommand = Command::PREPB; - currentRefreshPayload = &refreshPayloads.at(it); - break; - } - } - return; } + + if (allBankPairsBusy) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalP2B(); + return; + } + + nextCommand = Command::REFP2B; + currentRefreshPayload = &refreshPayloads.at(currentIterator->front()); + for (auto *it : *currentIterator) + { + if (it->isActivated()) + { + nextCommand = Command::PREPB; + currentRefreshPayload = &refreshPayloads.at(it); + break; + } + } + return; } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 3320bcac..8acc44eb 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -121,37 +121,36 @@ void RefreshManagerPerBank::evaluate() (*currentIterator)->block(); skipSelection = true; } - } - return; - } - else // if (state == RmState::Pulledin) - { - bool allBanksBusy = true; - - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) - { - if ((*it)->isIdle()) - { - currentIterator = it; - allBanksBusy = false; - break; - } } - - if (allBanksBusy) - { - state = State::Regular; - timeForNextTrigger += memSpec.getRefreshIntervalPB(); - return; - } - - if ((*currentIterator)->isActivated()) - nextCommand = Command::PREPB; - else - nextCommand = Command::REFPB; - return; } + + // if (state == RmState::Pulledin) + bool allBanksBusy = true; + + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + { + if ((*it)->isIdle()) + { + currentIterator = it; + allBanksBusy = false; + break; + } + } + + if (allBanksBusy) + { + state = State::Regular; + timeForNextTrigger += memSpec.getRefreshIntervalPB(); + return; + } + + if ((*currentIterator)->isActivated()) + nextCommand = Command::PREPB; + else + nextCommand = Command::REFPB; + + return; } } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 560470e2..2259ccd1 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -107,26 +107,6 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No read row hit found or bank precharged return readBuffer[bankID].front(); } - if (!writeBuffer[bankID].empty()) - { - if (bankMachine.isActivated()) - { - // Search for write row hit - Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bankID]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } - } - // No write row hit found or bank precharged - return writeBuffer[bankID].front(); - } - else - return nullptr; - } - else - { if (!writeBuffer[bankID].empty()) { if (bankMachine.isActivated()) @@ -142,24 +122,40 @@ tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankM // No write row hit found or bank precharged return writeBuffer[bankID].front(); } - if (!readBuffer[bankID].empty()) - { - if (bankMachine.isActivated()) - { - // Search for read row hit - Row openRow = bankMachine.getOpenRow(); - for (auto it : readBuffer[bankID]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } - } - // No read row hit found or bank precharged - return readBuffer[bankID].front(); - } - else - return nullptr; + return nullptr; } + + if (!writeBuffer[bankID].empty()) + { + if (bankMachine.isActivated()) + { + // Search for write row hit + Row openRow = bankMachine.getOpenRow(); + for (auto *it : writeBuffer[bankID]) + { + if (ControllerExtension::getRow(*it) == openRow) + return it; + } + } + // No write row hit found or bank precharged + return writeBuffer[bankID].front(); + } + if (!readBuffer[bankID].empty()) + { + if (bankMachine.isActivated()) + { + // Search for read row hit + Row openRow = bankMachine.getOpenRow(); + for (auto *it : readBuffer[bankID]) + { + if (ControllerExtension::getRow(*it) == openRow) + return it; + } + } + // No read row hit found or bank precharged + return readBuffer[bankID].front(); + } + return nullptr; } bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const @@ -180,7 +176,7 @@ bool SchedulerGrpFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command comman return false; } - for (auto it : writeBuffer[bank.ID()]) + for (auto *it : writeBuffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -198,10 +194,9 @@ bool SchedulerGrpFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const { return readBuffer[bank.ID()].size() >= 2; } - else - { - return writeBuffer[bank.ID()].size() >= 2; - } + + return writeBuffer[bank.ID()].size() >= 2; + } const std::vector& SchedulerGrpFrFcfs::getBufferDepth() const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index eb207104..bad6859a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -113,25 +113,23 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban } return nullptr; } - else + + if (!writeBuffer[bankID].empty()) { - if (!writeBuffer[bankID].empty()) + if (bankMachine.isActivated()) { - if (bankMachine.isActivated()) + // Search for write row hit + Row openRow = bankMachine.getOpenRow(); + for (auto *it : writeBuffer[bankID]) { - // Search for write row hit - Row openRow = bankMachine.getOpenRow(); - for (auto *it : writeBuffer[bankID]) - { - if (ControllerExtension::getRow(*it) == openRow) - return it; - } + if (ControllerExtension::getRow(*it) == openRow) + return it; } - // No row hit found or bank precharged - return writeBuffer[bankID].front(); } - return nullptr; + // No row hit found or bank precharged + return writeBuffer[bankID].front(); } + return nullptr; } bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const @@ -151,7 +149,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command return false; } - for (auto it : writeBuffer[bank.ID()]) + for (auto *it : writeBuffer[bank.ID()]) { if (ControllerExtension::getRow(*it) == row) { @@ -159,8 +157,8 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command if (rowHitCounter == 2) return true; } - } - return false; + } + return false; } bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index fed6a3c8..5e5b20d1 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -162,8 +162,7 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) const // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. for (const auto &it : vXor) { - uint64_t xoredBit; - xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } @@ -207,8 +206,7 @@ unsigned AddressDecoder::decodeChannel(uint64_t encAddr) const // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. for (const auto &it : vXor) { - uint64_t xoredBit; - xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + uint64_t xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); encAddr &= ~(UINT64_C(1) << it.first); encAddr |= xoredBit << it.first; } diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index 9aaf98ae..c40ce13c 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -123,8 +123,8 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) if (phase == HIT_HANDLING) // direct hit, account for the hit delay { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); hitQueue.emplace_back(index, tag, &trans); @@ -134,8 +134,8 @@ void Cache::peqCallback(tlm_generic_payload &trans, const tlm_phase &phase) { accessCacheAndSendResponse(trans); - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); auto mshrIt = std::find_if(mshrQueue.begin(), mshrQueue.end(), @@ -166,8 +166,8 @@ void Cache::fetchLineAndSendEndRequest(tlm_generic_payload &trans) { if (hasBufferSpace()) { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); auto mshrEntry = @@ -290,8 +290,8 @@ bool Cache::isHit(index_t index, tag_t tag) const bool Cache::isHit(uint64_t address) const { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(address); return isHit(index, tag); @@ -360,7 +360,7 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // There are still entries in mshrQueue to the oldest line -> do not evict it return nullptr; } - else if (std::find_if(hitQueue.begin(), hitQueue.end(), + if (std::find_if(hitQueue.begin(), hitQueue.end(), [index, oldestLine](const BufferEntry &entry) { return (index == entry.index) && (oldestLine.tag == entry.tag); }) != hitQueue.end()) { @@ -413,8 +413,8 @@ void Cache::processMshrQueue() // Note: This is the same address for all entries in the requests list uint64_t alignedAddress = getAlignedAddress(mshrIt->requestList.front()->get_address()); - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(alignedAddress); // Search through the writeBuffer in reverse order to get the most recent entry. @@ -515,8 +515,8 @@ void Cache::processWriteBuffer() /// Fill allocated cache line with data from memory void Cache::fillLine(tlm_generic_payload &trans) { - index_t index; - tag_t tag; + index_t index = 0; + tag_t tag = 0; std::tie(index, tag, std::ignore) = decodeAddress(trans.get_address()); CacheLine &allocatedLine = diff --git a/src/simulator/simulator/request/Request.h b/src/simulator/simulator/request/Request.h index bc26c785..730236ff 100644 --- a/src/simulator/simulator/request/Request.h +++ b/src/simulator/simulator/request/Request.h @@ -46,8 +46,8 @@ struct Request Write, Stop } command; - uint64_t address; - std::size_t length; + uint64_t address{}; + std::size_t length{}; sc_core::sc_time delay; std::vector data; }; From a9759f51fa14e5fb27ef7546732999b45068d4fe Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 16 May 2023 09:44:42 +0200 Subject: [PATCH 07/16] Enable warnings in dev preset and fix them --- CMakePresets.json | 3 ++- .../configuration/memspec/MemSpecLPDDR5.cpp | 16 ++++++++-------- src/libdramsys/DRAMSys/common/TlmRecorder.h | 3 +-- src/libdramsys/DRAMSys/common/dramExtensions.h | 5 +---- src/libdramsys/DRAMSys/common/utils.h | 2 +- .../DRAMSys/configuration/memspec/MemSpec.h | 4 ++-- .../configuration/memspec/MemSpecDDR3.cpp | 12 ++++++------ .../configuration/memspec/MemSpecDDR4.cpp | 4 ++-- .../configuration/memspec/MemSpecGDDR5.cpp | 2 +- .../configuration/memspec/MemSpecGDDR5X.cpp | 2 +- .../configuration/memspec/MemSpecGDDR6.cpp | 6 +++--- .../configuration/memspec/MemSpecHBM2.cpp | 2 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 8 ++++---- .../configuration/memspec/MemSpecSTTMRAM.cpp | 10 +++++----- .../configuration/memspec/MemSpecWideIO.cpp | 12 ++++++------ .../configuration/memspec/MemSpecWideIO2.cpp | 4 ++-- .../DRAMSys/controller/BankMachine.cpp | 2 +- src/libdramsys/DRAMSys/controller/BankMachine.h | 2 +- src/libdramsys/DRAMSys/controller/Command.h | 2 +- src/libdramsys/DRAMSys/controller/Controller.cpp | 12 +++++++----- .../DRAMSys/controller/ControllerRecordable.cpp | 9 +++++---- src/libdramsys/DRAMSys/controller/ManagerIF.h | 2 +- .../DRAMSys/controller/cmdmux/CmdMuxIF.h | 2 +- .../DRAMSys/controller/cmdmux/CmdMuxOldest.h | 4 ++-- .../DRAMSys/controller/cmdmux/CmdMuxStrict.h | 4 ++-- .../controller/powerdown/PowerDownManagerDummy.h | 2 +- .../powerdown/PowerDownManagerStaggered.cpp | 2 +- .../powerdown/PowerDownManagerStaggered.h | 2 +- .../controller/refresh/RefreshManagerAllBank.cpp | 4 ++-- .../controller/refresh/RefreshManagerAllBank.h | 2 +- .../controller/refresh/RefreshManagerDummy.h | 2 +- .../refresh/RefreshManagerPer2Bank.cpp | 2 +- .../controller/refresh/RefreshManagerPer2Bank.h | 2 +- .../controller/refresh/RefreshManagerPerBank.cpp | 2 +- .../controller/refresh/RefreshManagerPerBank.h | 2 +- .../refresh/RefreshManagerSameBank.cpp | 2 +- .../controller/refresh/RefreshManagerSameBank.h | 2 +- .../DRAMSys/controller/respqueue/RespQueueFifo.h | 2 +- .../DRAMSys/controller/respqueue/RespQueueIF.h | 2 +- .../controller/respqueue/RespQueueReorder.h | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 4 ++-- .../DRAMSys/controller/scheduler/SchedulerFifo.h | 10 +++++----- .../controller/scheduler/SchedulerFrFcfs.cpp | 4 ++-- .../controller/scheduler/SchedulerFrFcfs.h | 10 +++++----- .../controller/scheduler/SchedulerFrFcfsGrp.cpp | 4 ++-- .../controller/scheduler/SchedulerFrFcfsGrp.h | 10 +++++----- .../controller/scheduler/SchedulerGrpFrFcfs.h | 10 +++++----- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 4 ++-- .../controller/scheduler/SchedulerGrpFrFcfsWm.h | 10 +++++----- .../DRAMSys/controller/scheduler/SchedulerIF.h | 10 +++++----- src/libdramsys/DRAMSys/simulation/Arbiter.cpp | 6 +++--- src/libdramsys/DRAMSys/simulation/Arbiter.h | 6 +++--- src/libdramsys/DRAMSys/simulation/DRAMSys.cpp | 4 ++-- src/libdramsys/DRAMSys/simulation/DRAMSys.h | 2 +- src/libdramsys/DRAMSys/simulation/dram/Dram.cpp | 6 +++--- src/simulator/simulator/EccModule.cpp | 11 ++++++----- .../simulator/generator/RandomProducer.cpp | 2 +- .../simulator/generator/SequentialProducer.cpp | 4 ++-- .../simulator/generator/TrafficGenerator.cpp | 10 +++++----- src/simulator/simulator/hammer/RowHammer.cpp | 2 +- src/simulator/simulator/player/StlPlayer.cpp | 12 ++++++------ src/simulator/simulator/request/Request.h | 4 ++-- .../simulator/request/RequestIssuer.cpp | 7 ++----- tests/tests_configuration/test_configuration.cpp | 10 +++++++++- tests/tests_dramsys/AddressDecoderTests.cpp | 2 +- tests/tests_simulator/cache/TargetMemory.cpp | 6 +++--- tests/tests_simulator/cache/TargetMemory.h | 2 +- 67 files changed, 172 insertions(+), 166 deletions(-) diff --git a/CMakePresets.json b/CMakePresets.json index 6acf65ad..3bd3c6fc 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -69,7 +69,8 @@ "std" ], "cacheVariables": { - "CMAKE_BUILD_TYPE": "Debug" + "CMAKE_BUILD_TYPE": "Debug", + "CMAKE_CXX_FLAGS": "-Wall -Wextra -Wpedantic" } } ] diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index a34d70ba..55063551 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -59,30 +59,30 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIpb")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCab")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCpb")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPab")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPpb")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCpb")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCab")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD_L (tCK * memSpec.memtimingspec.entries.at("RCD_L")), tRCD_S (tCK * memSpec.memtimingspec.entries.at("RCD_S")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), - //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), tRL (tCK * memSpec.memtimingspec.entries.at("RL")), + //tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), + tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), //tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), //tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tRBTP (tCK * memSpec.memtimingspec.entries.at("RBTP")), tWL (tCK * memSpec.memtimingspec.entries.at("WL")), + tWR (tCK * memSpec.memtimingspec.entries.at("WR")), //tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), //tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tWR (tCK * memSpec.memtimingspec.entries.at("WR")), + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), //tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), //tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), //tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), @@ -104,10 +104,10 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), tBURST16(tCK * 16 / dataRate), tBURST32(tCK * 32 / dataRate), - bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)) + bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { commandLengthInCycles[Command::ACT] = 2; diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 17bfcbd3..6a4a8d04 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -89,6 +89,7 @@ public: void finalize(); private: + std::string name; const Configuration& config; const MemSpec& memSpec; @@ -131,8 +132,6 @@ private: std::vector recordedPhases; }; - std::string name; - std::string mcconfig, memspec, traces; void prepareSqlStatements(); diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 34c479da..44745262 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -299,10 +299,7 @@ public: return new EccExtension; } - void copy_from(tlm_extension_base const &ext) override - { - auto const &cpyFrom = dynamic_cast(ext); - } + void copy_from([[maybe_unused]] tlm_extension_base const & ext) override {} }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index 1f3de24b..3cc9de21 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -61,7 +61,7 @@ public: [[nodiscard]] bool intersects(const TimeInterval &other) const; }; -constexpr const char headline[] = +constexpr const std::string_view headline = "==========================================================================="; std::string getPhaseName(const tlm::tlm_phase &phase); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 75979552..25706279 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -102,8 +102,8 @@ public: [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - [[nodiscard]] sc_core::sc_time getCommandLength(Command /*command*/) const; - [[nodiscard]] double getCommandLengthInCycles(Command /*command*/) const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const; + [[nodiscard]] double getCommandLengthInCycles(Command command) const; [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index a46cb218..9aeff6b5 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -61,7 +61,6 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,16 +70,17 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), - tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), + tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tREFPDEN (tCK * memSpec.memtimingspec.entries.at("REFPDEN")), @@ -127,7 +127,7 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecDDR3::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -156,7 +156,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 8e86697b..cae2ed1e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -146,7 +146,7 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -174,7 +174,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 62c38281..a8999f80 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 88fac485..f536f8b9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -162,7 +162,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 94fb972b..23fae0c4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -60,7 +60,6 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at( "nbrOfBankGroups") * memSpec.memarchitecturespec.entries.at("nbrOfRanks"), memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), @@ -96,7 +95,8 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) tACTPDE (tCK * memSpec.memtimingspec.entries.at("ACTPDE")), tPREPDE (tCK * memSpec.memtimingspec.entries.at("PREPDE")), tREFPDE (tCK * memSpec.memtimingspec.entries.at("REFPDE")), - tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) + tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")), + per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; @@ -175,7 +175,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa throw; } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 431ae424..dc4a3700 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -163,7 +163,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload throw; } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index a1b1fe1f..fa59ff5b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -62,12 +62,12 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) tREFIpb (tCK * memSpec.memtimingspec.entries.at("REFIPB")), tRFCab (tCK * memSpec.memtimingspec.entries.at("RFCAB")), tRFCpb (tCK * memSpec.memtimingspec.entries.at("RFCPB")), + tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRPab (tCK * memSpec.memtimingspec.entries.at("RPAB")), tRPpb (tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tRCpb (tCK * memSpec.memtimingspec.entries.at("RCPB")), + tRCab (tCK * memSpec.memtimingspec.entries.at("RCAB")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), - tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), @@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb + tCK; @@ -166,7 +166,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index e2d7aa2d..41b93a5a 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -61,7 +61,6 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tPD (tCKE), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -71,14 +70,15 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXS (tCK * memSpec.memtimingspec.entries.at("XS")), + tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), - tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), - tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tXPDLL (tCK * memSpec.memtimingspec.entries.at("XPDLL")), tXSDLL (tCK * memSpec.memtimingspec.entries.at("XSDLL")), + tAL (tCK * memSpec.memtimingspec.entries.at("AL")), tACTPDEN (tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), tPRPDEN (tCK * memSpec.memtimingspec.entries.at("PRPDEN")), tRTRS (tCK * memSpec.memtimingspec.entries.at("RTRS")) @@ -104,7 +104,7 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecSTTMRAM::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -129,7 +129,7 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl return SC_ZERO_TIME; } -TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm::tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL, tRL + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index f78bd97e..0912ef88 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -60,8 +60,6 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) memSpec.memarchitecturespec.entries.at("nbrOfDevices")), tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")), tCKESR (tCK * memSpec.memtimingspec.entries.at("CKESR")), - tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tAC (tCK * memSpec.memtimingspec.entries.at("AC")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), @@ -70,11 +68,13 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) tWR (tCK * memSpec.memtimingspec.entries.at("WR")), tXP (tCK * memSpec.memtimingspec.entries.at("XP")), tXSR (tCK * memSpec.memtimingspec.entries.at("XSR")), - tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), - tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")), tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")), + tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), + tAC (tCK * memSpec.memtimingspec.entries.at("AC")), + tCCD_R (tCK * memSpec.memtimingspec.entries.at("CCD_R")), + tCCD_W (tCK * memSpec.memtimingspec.entries.at("CCD_W")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tTAW (tCK * memSpec.memtimingspec.entries.at("TAW")), tWTR (tCK * memSpec.memtimingspec.entries.at("WTR")), @@ -133,7 +133,7 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecWideIO::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB || command == Command::PREAB) return tRP; @@ -161,7 +161,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo throw; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tAC, tRL + tAC + burstDuration}; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index fd193b81..e4d78e94 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload & /*payload*/) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::PREPB) return tRPpb; @@ -151,7 +151,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl throw; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload & /*payload*/) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_unused]] const tlm_generic_payload & payload) const { if (command == Command::RD || command == Command::RDA) return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 3774430c..fb74fe6d 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -45,7 +45,7 @@ namespace DRAMSys { BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) - : scheduler(scheduler), memSpec(*config.memSpec), bank(bank), + : memSpec(*config.memSpec), scheduler(scheduler), bank(bank), bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)), refreshManagement(config.refreshManagement) {} diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 39a04f2b..39da86db 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -53,7 +53,7 @@ class BankMachine : public ManagerIF { public: CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override; + void update(Command command) override; void block(); [[nodiscard]] Rank getRank() const; diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 4e43523d..c6f520c5 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -84,7 +84,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 26 DECLARE_EXTENDED_PHASE(END_SREF); // 27 #ifdef DRAMPOWER -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase /*phase*/ /*phase*/); +DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); #endif bool phaseHasDataStrobe(tlm::tlm_phase phase); diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index dbc0f7c3..d689e6ab 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -80,10 +80,10 @@ namespace DRAMSys { Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : - ControllerIF(name, config), addressDecoder(addressDecoder), - thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), - phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw), - blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay), + ControllerIF(name, config), thinkDelayFw(config.thinkDelayFw), + thinkDelayBw(config.thinkDelayBw), phyDelayFw(config.phyDelayFw), + phyDelayBw(config.phyDelayBw), blockingReadDelay(config.blockingReadDelay), + blockingWriteDelay(config.blockingWriteDelay), addressDecoder(addressDecoder), minBytesPerBurst(config.memSpec->defaultBytesPerBurst), maxBytesPerBurst(config.memSpec->maxBytesPerBurst) { @@ -440,7 +440,9 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& return TLM_ACCEPTED; } -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& /*trans*/,tlm_phase& /*phase*/, sc_time& /*delay*/) +tlm_sync_enum Controller::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index 16f86af0..d82ba70f 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -45,8 +45,8 @@ namespace DRAMSys ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), - activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), enableWindowing(config.enableWindowing), - windowSizeTime(config.windowSize * memSpec.tCK) + windowSizeTime(config.windowSize * memSpec.tCK), activeTimeMultiplier(config.memSpec->tCK / config.memSpec->dataRate), + enableWindowing(config.enableWindowing) { if (enableWindowing) { @@ -65,8 +65,9 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload& trans, return Controller::nb_transport_fw(trans, phase, delay); } -tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload& /*trans*/, - tlm_phase& /*phase*/, sc_time& /*delay*/) +tlm_sync_enum ControllerRecordable::nb_transport_bw([[maybe_unused]] tlm_generic_payload &trans, + [[maybe_unused]] tlm_phase &phase, + [[maybe_unused]] sc_time &delay) { SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called"); return TLM_ACCEPTED; diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 99e95da6..06a8afaa 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -45,7 +45,7 @@ class ManagerIF public: virtual void evaluate() = 0; virtual CommandTuple::Type getNextCommand() = 0; - virtual void update(Command /*command*/) = 0; + virtual void update(Command command) = 0; virtual ~ManagerIF() = default; }; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index 996295e5..a3070f8c 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -44,7 +44,7 @@ class CmdMuxIF { public: virtual ~CmdMuxIF() = default; - virtual CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) = 0; + virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index c52ffdf0..6ff5772c 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -45,7 +45,7 @@ class CmdMuxOldest : public CmdMuxIF { public: explicit CmdMuxOldest(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; @@ -57,7 +57,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF { public: explicit CmdMuxOldestRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: const MemSpec& memSpec; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index eb1b5b4a..2b98bc9e 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -45,7 +45,7 @@ class CmdMuxStrict : public CmdMuxIF { public: explicit CmdMuxStrict(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; @@ -57,7 +57,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF { public: explicit CmdMuxStrictRasCas(const Configuration& config); - CommandTuple::Type selectCommand(const ReadyCommands & /*readyCommands*/) override; + CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) override; private: uint64_t nextPayloadID = 1; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index f874a198..8e81f472 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -50,7 +50,7 @@ public: void triggerInterruption() override {} CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override {} + void update([[maybe_unused]] Command command) override {} void evaluate() override {} }; diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index 63bbc485..48d160cd 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -43,7 +43,7 @@ namespace DRAMSys { PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector& bankMachinesOnRank, - Rank rank, CheckerIF& checker) + Rank rank, [[maybe_unused]] CheckerIF& checker) : bankMachinesOnRank(bankMachinesOnRank) { setUpDummy(powerDownPayload, UINT64_MAX - 1, rank); diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index 5b9175d9..54cc6793 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -57,7 +57,7 @@ public: void triggerInterruption() override; CommandTuple::Type getNextCommand() override; - void update(Command /*command*/) override; + void update(Command command) override; void evaluate() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index 333ef9f1..de5fa193 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -46,8 +46,8 @@ namespace DRAMSys RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), - memSpec(*config.memSpec), maxPostponed(static_cast(config.refreshMaxPostponed)), + : memSpec(*config.memSpec), bankMachinesOnRank(bankMachinesOnRank), + powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed)), maxPulledin(-static_cast(config.refreshMaxPulledin)), refreshManagement(config.refreshManagement) { timeForNextTrigger = getTimeForFirstTrigger(memSpec.tCK, memSpec.getRefreshIntervalAB(), diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 7ccd7ecd..0b287f03 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -58,7 +58,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 72328a5e..18c92d81 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF public: CommandTuple::Type getNextCommand() override; void evaluate() override {} - void update(Command /*command*/) override {} + void update([[maybe_unused]] Command command) override {} sc_core::sc_time getTimeForNextTrigger() override; private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index e1a90770..a4816f74 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank / 2)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank / 2)) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index 88e7a489..548add98 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index 8acc44eb..581e1d2f 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -45,7 +45,7 @@ namespace DRAMSys RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerRank)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerRank)) { diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index 294b9412..fb955d99 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -60,7 +60,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index 802103c0..23eff9d9 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -46,7 +46,7 @@ namespace DRAMSys RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) - : powerDownManager(powerDownManager), memSpec(*config.memSpec), + : memSpec(*config.memSpec), powerDownManager(powerDownManager), maxPostponed(static_cast(config.refreshMaxPostponed * memSpec.banksPerGroup)), maxPulledin(-static_cast(config.refreshMaxPulledin * memSpec.banksPerGroup)), refreshManagement(config.refreshManagement) diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index 28b7d01d..70a98f99 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -59,7 +59,7 @@ public: CommandTuple::Type getNextCommand() override; void evaluate() override; - void update(Command /*command*/) override; + void update(Command command) override; sc_core::sc_time getTimeForNextTrigger() override; private: diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index cce032be..f6a0f53a 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -48,7 +48,7 @@ namespace DRAMSys class RespQueueFifo final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index ec95ee23..30a6c53b 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -44,7 +44,7 @@ namespace DRAMSys class RespQueueIF { public: - virtual void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) = 0; + virtual void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) = 0; virtual tlm::tlm_generic_payload* nextPayload() = 0; [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; virtual ~RespQueueIF() = default; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index 4a355b17..cb698438 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -47,7 +47,7 @@ namespace DRAMSys class RespQueueReorder final : public RespQueueIF { public: - void insertPayload(tlm::tlm_generic_payload* /*payload*/, sc_core::sc_time /*strobeEnd*/) override; + void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) override; tlm::tlm_generic_payload* nextPayload() override; [[nodiscard]] sc_core::sc_time getTriggerTime() const override; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 10df01b8..f590c32b 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -80,7 +80,7 @@ tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachin return nullptr; } -bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { if (buffer[bank.ID()].size() >= 2) { @@ -91,7 +91,7 @@ bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) co return false; } -bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFifo::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return buffer[bank.ID()].size() >= 2; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index 9bcb672d..7e922d93 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -53,11 +53,11 @@ class SchedulerFifo final : public SchedulerIF public: explicit SchedulerFifo(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index f71f0f68..fa5e854a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -101,7 +101,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach return nullptr; } -bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; for (auto *it : buffer[bank.ID()]) @@ -116,7 +116,7 @@ bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, tlm_command command) return false; } -bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfs::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return (buffer[bank.ID()].size() >= 2); } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index e317b044..02215742 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerFrFcfs final : public SchedulerIF public: explicit SchedulerFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index 6017dc28..fa285072 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -126,7 +126,7 @@ tlm_generic_payload* SchedulerFrFcfsGrp::getNextRequest(const BankMachine& bankM return nullptr; } -bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; for (auto *it : buffer[bank.ID()]) @@ -141,7 +141,7 @@ bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row, tlm_command comman return false; } -bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, tlm_command command) const +bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm_command command) const { return buffer[bank.ID()].size() >= 2; } diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 1f0536d7..282ecf5e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -53,11 +53,11 @@ class SchedulerFrFcfsGrp final : public SchedulerIF public: explicit SchedulerFrFcfsGrp(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index 77e7e7ba..4be55fd3 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -53,11 +53,11 @@ class SchedulerGrpFrFcfs final : public SchedulerIF public: explicit SchedulerGrpFrFcfs(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index bad6859a..085fef00 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -132,7 +132,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban return nullptr; } -bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm::tlm_command command) const { unsigned rowHitCounter = 0; if (!writeMode) @@ -161,7 +161,7 @@ bool SchedulerGrpFrFcfsWm::hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command return false; } -bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, tlm::tlm_command command) const +bool SchedulerGrpFrFcfsWm::hasFurtherRequest(Bank bank, [[maybe_unused]] tlm::tlm_command command) const { if (!writeMode) return (readBuffer[bank.ID()].size() >= 2); diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index fb4b2c2d..f9e6d207 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -54,11 +54,11 @@ class SchedulerGrpFrFcfsWm final : public SchedulerIF public: explicit SchedulerGrpFrFcfsWm(const Configuration& config); [[nodiscard]] bool hasBufferSpace() const override; - void storeRequest(tlm::tlm_generic_payload& /*payload*/) override; - void removeRequest(tlm::tlm_generic_payload& /*payload*/) override; - [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const override; - [[nodiscard]] bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const override; - [[nodiscard]] bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const override; + void storeRequest(tlm::tlm_generic_payload& payload) override; + void removeRequest(tlm::tlm_generic_payload& payload) override; + [[nodiscard]] tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const override; + [[nodiscard]] bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const override; + [[nodiscard]] bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const override; [[nodiscard]] const std::vector& getBufferDepth() const override; private: diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index f7b2577c..da3639b4 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -50,11 +50,11 @@ class SchedulerIF public: virtual ~SchedulerIF() = default; [[nodiscard]] virtual bool hasBufferSpace() const = 0; - virtual void storeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; - virtual void removeRequest(tlm::tlm_generic_payload& /*payload*/) = 0; - [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& /*bankMachine*/) const = 0; - [[nodiscard]] virtual bool hasFurtherRowHit(Bank /*bank*/, Row /*row*/, tlm::tlm_command /*command*/) const = 0; - [[nodiscard]] virtual bool hasFurtherRequest(Bank /*bank*/, tlm::tlm_command /*command*/) const = 0; + virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0; + virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0; + [[nodiscard]] virtual tlm::tlm_generic_payload* getNextRequest(const BankMachine& bankMachine) const = 0; + [[nodiscard]] virtual bool hasFurtherRowHit(Bank bank, Row row, tlm::tlm_command command) const = 0; + [[nodiscard]] virtual bool hasFurtherRequest(Bank bank, tlm::tlm_command command) const = 0; [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index 6517e8fa..f3a7e1c8 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -156,7 +156,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload& trans, return TLM_ACCEPTED; } -tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload, +tlm_sync_enum Arbiter::nb_transport_bw([[maybe_unused]] int id, tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { PRINTDEBUGMESSAGE(name(), "[bw] " + getPhaseName(phase) + " notification in " + @@ -165,7 +165,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int /*id*/, tlm_generic_payload& payload, return TLM_ACCEPTED; } -void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) +void Arbiter::b_transport([[maybe_unused]] int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { trans.set_address(trans.get_address() - addressOffset); @@ -173,7 +173,7 @@ void Arbiter::b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core:: iSocket[static_cast(decodedAddress.channel)]->b_transport(trans, delay); } -unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans) +unsigned int Arbiter::transport_dbg([[maybe_unused]] int id, tlm::tlm_generic_payload& trans) { trans.set_address(trans.get_address() - addressOffset); diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index bc90e2c1..06ec9108 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -87,10 +87,10 @@ protected: tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& fwDelay); - tlm::tlm_sync_enum nb_transport_bw(int /*id*/, tlm::tlm_generic_payload &payload, + tlm::tlm_sync_enum nb_transport_bw(int id, tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); - void b_transport(int /*id*/, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); - unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans); + void b_transport(int id, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); + unsigned int transport_dbg(int id, tlm::tlm_generic_payload& trans); const sc_core::sc_time tCK; const sc_core::sc_time arbitrationDelayFw; diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index 6c318b48..8ebdd133 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -234,9 +234,9 @@ void DRAMSys::bindSockets() } } -void DRAMSys::report(const std::string& message) +void DRAMSys::report(std::string_view message) { - PRINTDEBUGMESSAGE(name(), message); + PRINTDEBUGMESSAGE(name(), message.data()); std::cout << message << std::endl; } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 0df0356b..a641ec9c 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -99,7 +99,7 @@ protected: std::unique_ptr addressDecoder; - void report(const std::string& message); + void report(std::string_view message); void bindSockets(); private: diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index c0a988eb..db604fe2 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -68,8 +68,8 @@ namespace DRAMSys Dram::Dram(const sc_module_name& name, const Configuration& config) - : sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode), - powerAnalysis(config.powerAnalysis), useMalloc(config.useMalloc) + : sc_module(name), memSpec(*config.memSpec), storeMode(config.storeMode), powerAnalysis(config.powerAnalysis), + useMalloc(config.useMalloc), tSocket("socket") { uint64_t channelSize = memSpec.getSimMemSizeInBytes() / memSpec.numberOfChannels; if (storeMode == Configuration::StoreMode::Store) @@ -202,7 +202,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans) return 0; } -void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay) +void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& delay) { static bool printedWarning = false; diff --git a/src/simulator/simulator/EccModule.cpp b/src/simulator/simulator/EccModule.cpp index cf1a25d0..5933d969 100644 --- a/src/simulator/simulator/EccModule.cpp +++ b/src/simulator/simulator/EccModule.cpp @@ -46,8 +46,8 @@ using namespace tlm; EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder) : sc_core::sc_module(name), payloadEventQueue(this, &EccModule::peqCallback), - addressDecoder(addressDecoder), - memoryManager(false) + memoryManager(false), + addressDecoder(addressDecoder) { iSocket.register_nb_transport_bw(this, &EccModule::nb_transport_bw); tSocket.register_nb_transport_fw(this, &EccModule::nb_transport_fw); @@ -94,12 +94,11 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ // Update the original address to account for the offsets cbPayload.set_address(addressDecoder.encodeAddress(decodedAddress)); - auto currentBlock = alignToBlock(decodedAddress.column); - // In case there is no entry yet. activeEccBlocks.try_emplace(decodedAddress.bank); #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = &cbPayload; @@ -160,8 +159,10 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); - auto currentBlock = alignToBlock(decodedAddress.column); + #ifdef ECC_ENABLE + auto currentBlock = alignToBlock(decodedAddress.column); + if (!activeEccBlock(decodedAddress.bank, decodedAddress.row, currentBlock)) { blockedRequest = pendingRequest; diff --git a/src/simulator/simulator/generator/RandomProducer.cpp b/src/simulator/simulator/generator/RandomProducer.cpp index b6a7001e..fafa99e9 100644 --- a/src/simulator/simulator/generator/RandomProducer.cpp +++ b/src/simulator/simulator/generator/RandomProducer.cpp @@ -48,10 +48,10 @@ RandomProducer::RandomProducer(uint64_t numRequests, : numberOfRequests(numRequests), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), generatorPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), dataLength(dataLength), dataAlignment(dataAlignment), + randomGenerator(this->seed), randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS), maxAddress.value_or((memorySize) - dataLength)) { diff --git a/src/simulator/simulator/generator/SequentialProducer.cpp b/src/simulator/simulator/generator/SequentialProducer.cpp index b39a6479..481b1808 100644 --- a/src/simulator/simulator/generator/SequentialProducer.cpp +++ b/src/simulator/simulator/generator/SequentialProducer.cpp @@ -51,9 +51,9 @@ SequentialProducer::SequentialProducer(uint64_t numRequests, maxAddress(maxAddress.value_or(memorySize - 1)), seed(seed.value_or(DEFAULT_SEED)), rwRatio(rwRatio), - randomGenerator(this->seed), generatorPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), - dataLength(dataLength) + dataLength(dataLength), + randomGenerator(this->seed) { if (minAddress > memorySize - 1) SC_REPORT_FATAL("TrafficGenerator", "minAddress is out of range."); diff --git a/src/simulator/simulator/generator/TrafficGenerator.cpp b/src/simulator/simulator/generator/TrafficGenerator.cpp index 644f57b3..3fc99b3d 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.cpp +++ b/src/simulator/simulator/generator/TrafficGenerator.cpp @@ -41,15 +41,15 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine unsigned int defaultDataLength, std::function transactionFinished, std::function terminateInitiator) - : consumer( + : stateTransistions(config.transitions), + consumer( config.name.c_str(), memoryManager, config.maxPendingReadRequests, config.maxPendingWriteRequests, [this] { return nextRequest(); }, std::move(transactionFinished), - std::move(terminateInitiator)), - stateTransistions(config.transitions) + std::move(terminateInitiator)) { unsigned int dataLength = config.dataLength.value_or(defaultDataLength); unsigned int dataAlignment = config.dataAlignment.value_or(dataLength); @@ -163,7 +163,7 @@ Request TrafficGenerator::nextRequest() auto newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; auto idleStateIt = idleStateClks.find(newState.value()); while (idleStateIt != idleStateClks.cend()) @@ -172,7 +172,7 @@ Request TrafficGenerator::nextRequest() newState = stateTransition(currentState); if (!newState.has_value()) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; currentState = newState.value(); idleStateIt = idleStateClks.find(newState.value()); diff --git a/src/simulator/simulator/hammer/RowHammer.cpp b/src/simulator/simulator/hammer/RowHammer.cpp index 4ca7d7b3..fe76f357 100644 --- a/src/simulator/simulator/hammer/RowHammer.cpp +++ b/src/simulator/simulator/hammer/RowHammer.cpp @@ -49,7 +49,7 @@ RowHammer::RowHammer(uint64_t numRequests, Request RowHammer::nextRequest() { if (generatedRequests >= numberOfRequests) - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; generatedRequests++; diff --git a/src/simulator/simulator/player/StlPlayer.cpp b/src/simulator/simulator/player/StlPlayer.cpp index d80a6157..3139cea9 100644 --- a/src/simulator/simulator/player/StlPlayer.cpp +++ b/src/simulator/simulator/player/StlPlayer.cpp @@ -47,15 +47,15 @@ StlPlayer::StlPlayer(std::string_view tracePath, unsigned int defaultDataLength, TraceType traceType, bool storageEnabled) - : traceFile(tracePath.data()), + : traceType(traceType), + storageEnabled(storageEnabled), playerPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), defaultDataLength(defaultDataLength), - traceType(traceType), - storageEnabled(storageEnabled), + traceFile(tracePath.data()), lineBuffers( {std::make_shared>(), std::make_shared>()}), - readoutBuffer(lineBuffers.at(0)), - parseBuffer(lineBuffers.at(1)) + parseBuffer(lineBuffers.at(1)), + readoutBuffer(lineBuffers.at(0)) { readoutBuffer->reserve(LINE_BUFFER_SIZE); parseBuffer->reserve(LINE_BUFFER_SIZE); @@ -90,7 +90,7 @@ Request StlPlayer::nextRequest() parserThread.join(); // The file is read in completely. Nothing more to do. - return Request{.command = Request::Command::Stop}; + return Request{Request::Command::Stop}; } } diff --git a/src/simulator/simulator/request/Request.h b/src/simulator/simulator/request/Request.h index 730236ff..61eccb0f 100644 --- a/src/simulator/simulator/request/Request.h +++ b/src/simulator/simulator/request/Request.h @@ -48,6 +48,6 @@ struct Request } command; uint64_t address{}; std::size_t length{}; - sc_core::sc_time delay; - std::vector data; + sc_core::sc_time delay{}; + std::vector data{}; }; diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index 8ae4417f..84c808dc 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -43,13 +43,13 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name, std::function transactionFinished, std::function terminate) : sc_module(name), + payloadEventQueue(this, &RequestIssuer::peqCallback), memoryManager(memoryManager), maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests), - nextRequest(std::move(nextRequest)), transactionFinished(std::move(transactionFinished)), terminate(std::move(terminate)), - payloadEventQueue(this, &RequestIssuer::peqCallback) + nextRequest(std::move(nextRequest)) { SC_THREAD(sendNextRequest); iSocket.register_nb_transport_bw(this, &RequestIssuer::nb_transport_bw); @@ -79,9 +79,6 @@ void RequestIssuer::sendNextRequest() tlm::tlm_phase phase = tlm::BEGIN_REQ; sc_core::sc_time delay = request.delay; - if (request.address == 0x4000f000) - int x = 0; - if (transactionsSent == 0) delay = sc_core::SC_ZERO_TIME; diff --git a/tests/tests_configuration/test_configuration.cpp b/tests/tests_configuration/test_configuration.cpp index 52cd12df..6e3fa4e9 100644 --- a/tests/tests_configuration/test_configuration.cpp +++ b/tests/tests_configuration/test_configuration.cpp @@ -87,7 +87,15 @@ protected: PowerDownPolicyType::NoPowerDown, ArbiterType::Simple, 128, - {}}; + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt, + std::nullopt}; DRAMSys::Config::SimConfig simConfig{0, false, diff --git a/tests/tests_dramsys/AddressDecoderTests.cpp b/tests/tests_dramsys/AddressDecoderTests.cpp index 1c49af9e..29794c50 100644 --- a/tests/tests_dramsys/AddressDecoderTests.cpp +++ b/tests/tests_dramsys/AddressDecoderTests.cpp @@ -47,8 +47,8 @@ protected: addressMappingJson(nlohmann::json::parse(addressMappingJsonString).at("addressmapping")), memSpecJson(nlohmann::json::parse(memSpecJsonString).at("memspec")), addressMappingConfig(addressMappingJson.get()), - memSpec(memSpecConfig), memSpecConfig(memSpecJson.get()), + memSpec(memSpecConfig), addressDecoder(addressMappingConfig, memSpec) { } diff --git a/tests/tests_simulator/cache/TargetMemory.cpp b/tests/tests_simulator/cache/TargetMemory.cpp index adf1af0f..b3f30353 100644 --- a/tests/tests_simulator/cache/TargetMemory.cpp +++ b/tests/tests_simulator/cache/TargetMemory.cpp @@ -49,9 +49,9 @@ TargetMemory::TargetMemory(const sc_core::sc_module_name &name, : sc_core::sc_module(name), tSocket("tSocket"), bufferSize(bufferSize), - peq(this, &TargetMemory::peqCallback), acceptDelay(acceptDelay), - memoryLatency(memoryLatency) + memoryLatency(memoryLatency), + peq(this, &TargetMemory::peqCallback) { tSocket.register_nb_transport_fw(this, &TargetMemory::nb_transport_fw); @@ -155,7 +155,7 @@ void TargetMemory::sendEndRequest(tlm::tlm_generic_payload &trans) bw_phase = tlm::END_REQ; delay = acceptDelay; - tlm::tlm_sync_enum status = tSocket->nb_transport_bw(trans, bw_phase, delay); + tSocket->nb_transport_bw(trans, bw_phase, delay); // Queue internal event to mark beginning of response delay = delay + memoryLatency; // MEMORY Latency diff --git a/tests/tests_simulator/cache/TargetMemory.h b/tests/tests_simulator/cache/TargetMemory.h index 40af3915..ba526a6c 100644 --- a/tests/tests_simulator/cache/TargetMemory.h +++ b/tests/tests_simulator/cache/TargetMemory.h @@ -65,7 +65,7 @@ private: void printBuffer(int max, int n); - static constexpr std::size_t SIZE = static_cast(64 * 1024); + static constexpr std::size_t SIZE = static_cast(64 * 1024); static constexpr std::size_t DEFAULT_BUFFER_SIZE = 8; const std::size_t bufferSize; From 093ee73d54ae277e9d58e95003556119b6fb26e8 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 16 May 2023 09:49:47 +0200 Subject: [PATCH 08/16] Add .clang-tidy and .clang-format configurations --- .clang-format | 12 ++++++++++++ .clang-tidy | 7 +++++++ extensions/apps/traceAnalyzer/.clang-format | 13 ------------- 3 files changed, 19 insertions(+), 13 deletions(-) create mode 100644 .clang-format create mode 100644 .clang-tidy delete mode 100644 extensions/apps/traceAnalyzer/.clang-format diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..1dd7cebc --- /dev/null +++ b/.clang-format @@ -0,0 +1,12 @@ +--- +AccessModifierOffset: '-4' +AllowShortFunctionsOnASingleLine: InlineOnly +AllowShortIfStatementsOnASingleLine: Never +BinPackArguments: 'false' +BinPackParameters: 'false' +BreakBeforeBraces: Allman +ColumnLimit: '100' +ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' +IndentWidth: '4' + +... diff --git a/.clang-tidy b/.clang-tidy new file mode 100644 index 00000000..33ff78e5 --- /dev/null +++ b/.clang-tidy @@ -0,0 +1,7 @@ +--- +Checks: 'clang-diagnostic-*,clang-analyzer-*,modernize-*,bugprone-*,concurrency-*,cppcoreguidelines-*,performance-*,portability-*,readability-*,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-identifier-length' +WarningsAsErrors: '' +HeaderFilterRegex: '' +AnalyzeTemporaryDtors: false +FormatStyle: file +... diff --git a/extensions/apps/traceAnalyzer/.clang-format b/extensions/apps/traceAnalyzer/.clang-format deleted file mode 100644 index 950e9ea8..00000000 --- a/extensions/apps/traceAnalyzer/.clang-format +++ /dev/null @@ -1,13 +0,0 @@ ---- -BasedOnStyle: LLVM -AccessModifierOffset: '-4' -AllowShortFunctionsOnASingleLine: None -AllowShortIfStatementsOnASingleLine: Never -AllowShortLoopsOnASingleLine: 'false' -AlwaysBreakTemplateDeclarations: 'true' -BreakBeforeBraces: Allman -ColumnLimit: '120' -IndentWidth: '4' -PointerAlignment: Right - -... From 32e828d2540c1080cbabf3a5f46ab61a9ad842e8 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 17 May 2023 11:23:38 +0200 Subject: [PATCH 09/16] Fix cppcoreguidelines-special-member-functions warnings --- src/libdramsys/DRAMSys/common/DebugManager.h | 2 ++ src/libdramsys/DRAMSys/common/TlmRecorder.h | 8 +++++--- src/libdramsys/DRAMSys/configuration/Configuration.h | 4 ---- src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h | 9 +++++++-- src/libdramsys/DRAMSys/controller/Controller.h | 6 ++++++ .../DRAMSys/controller/ControllerRecordable.h | 1 - src/libdramsys/DRAMSys/controller/ManagerIF.h | 10 +++++++++- src/libdramsys/DRAMSys/controller/checker/CheckerIF.h | 7 +++++++ src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h | 8 ++++++++ .../DRAMSys/controller/respqueue/RespQueueIF.h | 10 +++++++++- .../DRAMSys/controller/scheduler/BufferCounterIF.h | 8 ++++++++ .../DRAMSys/controller/scheduler/SchedulerIF.h | 8 ++++++++ src/libdramsys/DRAMSys/simulation/dram/Dram.h | 5 +++++ src/simulator/simulator/Initiator.h | 7 +++++++ src/simulator/simulator/MemoryManager.h | 5 +++++ src/simulator/simulator/request/RequestProducer.h | 7 +++++++ src/util/DRAMSys/util/json.h | 6 +++++- 17 files changed, 98 insertions(+), 13 deletions(-) diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index cee92445..0c93e050 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -64,6 +64,8 @@ private: public: DebugManager(const DebugManager&) = delete; DebugManager& operator=(const DebugManager&) = delete; + DebugManager(DebugManager&&) = delete; + DebugManager& operator=(DebugManager&&) = delete; void setup(bool _debugEnabled, bool _writeToConsole, bool _writeToFile); diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 6a4a8d04..4cbc705d 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -63,8 +63,11 @@ class TlmRecorder { public: TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName); - TlmRecorder(const TlmRecorder&) = delete; - TlmRecorder(TlmRecorder&&) = default; + TlmRecorder(const TlmRecorder &) = delete; + TlmRecorder(TlmRecorder &&) = default; + TlmRecorder &operator=(const TlmRecorder &) = delete; + TlmRecorder &operator=(TlmRecorder &&) = delete; + ~TlmRecorder() = default; void recordMcConfig(std::string _mcconfig) { @@ -95,7 +98,6 @@ private: struct Transaction { - Transaction(const Transaction& other) = default; Transaction(uint64_t id, uint64_t address, unsigned int dataLength, char cmd, const sc_core::sc_time& timeOfGeneration, Thread thread, Channel channel) : id(id), address(address), dataLength(dataLength), cmd(cmd), timeOfGeneration(timeOfGeneration), diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index 5cdfb938..55700028 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -55,10 +55,6 @@ namespace DRAMSys class Configuration { public: - Configuration() = default; - Configuration(const Configuration&) = delete; - Configuration& operator=(const Configuration &) = delete; - // MCConfig: enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open; enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp, GrpFrFcfs, GrpFrFcfsWm} scheduler = Scheduler::FrFcfs; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 25706279..a808d241 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -54,6 +54,10 @@ namespace DRAMSys class MemSpec { public: + MemSpec &operator=(const MemSpec &) = delete; + MemSpec &operator=(MemSpec &&) = delete; + virtual ~MemSpec() = default; + const unsigned numberOfChannels; const unsigned pseudoChannelsPerChannel; const unsigned ranksPerChannel; @@ -84,8 +88,6 @@ public: WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, HBM3, STTMRAM } memoryType; - virtual ~MemSpec() = default; - [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const; [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const; @@ -115,6 +117,9 @@ protected: unsigned banksPerChannel, unsigned bankGroupsPerChannel, unsigned devicesPerRank); + MemSpec(const MemSpec &) = default; + MemSpec(MemSpec &&) = default; + // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; sc_core::sc_time burstDuration; diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index f2a1ea60..5913083e 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -118,7 +118,13 @@ private: class MemoryManager : public tlm::tlm_mm_interface { public: + MemoryManager() = default; + MemoryManager(const MemoryManager &) = delete; + MemoryManager(MemoryManager &&) = delete; + MemoryManager &operator=(const MemoryManager &) = delete; + MemoryManager &operator=(MemoryManager &&) = delete; ~MemoryManager() override; + tlm::tlm_generic_payload& allocate(); void free(tlm::tlm_generic_payload* trans) override; diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 91fd3832..0445179c 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -49,7 +49,6 @@ class ControllerRecordable final : public Controller public: ControllerRecordable(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder); - ~ControllerRecordable() override = default; protected: tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 06a8afaa..b4e1c380 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -42,11 +42,19 @@ namespace DRAMSys class ManagerIF { +protected: + ManagerIF(const ManagerIF &) = default; + ManagerIF(ManagerIF &&) = default; + ManagerIF &operator=(const ManagerIF &) = default; + ManagerIF &operator=(ManagerIF &&) = default; + public: + ManagerIF() = default; + virtual ~ManagerIF() = default; + virtual void evaluate() = 0; virtual CommandTuple::Type getNextCommand() = 0; virtual void update(Command command) = 0; - virtual ~ManagerIF() = default; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index 35f0ecd4..6580e910 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -44,7 +44,14 @@ namespace DRAMSys class CheckerIF { +protected: + CheckerIF(const CheckerIF &) = default; + CheckerIF(CheckerIF &&) = default; + CheckerIF &operator=(const CheckerIF &) = default; + CheckerIF &operator=(CheckerIF &&) = default; + public: + CheckerIF() = default; virtual ~CheckerIF() = default; [[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index a3070f8c..c032a159 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -42,8 +42,16 @@ namespace DRAMSys class CmdMuxIF { +protected: + CmdMuxIF(const CmdMuxIF &) = default; + CmdMuxIF(CmdMuxIF &&) = default; + CmdMuxIF &operator=(const CmdMuxIF &) = default; + CmdMuxIF &operator=(CmdMuxIF &&) = default; + public: + CmdMuxIF() = default; virtual ~CmdMuxIF() = default; + virtual CommandTuple::Type selectCommand(const ReadyCommands & readyCommands) = 0; }; diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index 30a6c53b..dad6725a 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -43,11 +43,19 @@ namespace DRAMSys class RespQueueIF { +protected: + RespQueueIF(const RespQueueIF &) = default; + RespQueueIF(RespQueueIF &&) = default; + RespQueueIF &operator=(const RespQueueIF &) = default; + RespQueueIF &operator=(RespQueueIF &&) = default; + public: + RespQueueIF() = default; + virtual ~RespQueueIF() = default; + virtual void insertPayload(tlm::tlm_generic_payload* payload, sc_core::sc_time strobeEnd) = 0; virtual tlm::tlm_generic_payload* nextPayload() = 0; [[nodiscard]] virtual sc_core::sc_time getTriggerTime() const = 0; - virtual ~RespQueueIF() = default; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h index fd4a6fbe..02357545 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h @@ -43,8 +43,16 @@ namespace DRAMSys class BufferCounterIF { +protected: + BufferCounterIF(const BufferCounterIF &) = default; + BufferCounterIF(BufferCounterIF &&) = default; + BufferCounterIF &operator=(const BufferCounterIF &) = default; + BufferCounterIF &operator=(BufferCounterIF &&) = default; + public: + BufferCounterIF() = default; virtual ~BufferCounterIF() = default; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(const tlm::tlm_generic_payload& trans) = 0; virtual void removeRequest(const tlm::tlm_generic_payload& trans) = 0; diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index da3639b4..0aed1e9e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -47,8 +47,16 @@ class BankMachine; class SchedulerIF { +protected: + SchedulerIF(const SchedulerIF &) = default; + SchedulerIF(SchedulerIF &&) = default; + SchedulerIF &operator=(const SchedulerIF &) = default; + SchedulerIF &operator=(SchedulerIF &&) = default; + public: + SchedulerIF() = default; virtual ~SchedulerIF() = default; + [[nodiscard]] virtual bool hasBufferSpace() const = 0; virtual void storeRequest(tlm::tlm_generic_payload& payload) = 0; virtual void removeRequest(tlm::tlm_generic_payload& payload) = 0; diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.h b/src/libdramsys/DRAMSys/simulation/dram/Dram.h index 9227d391..acf16459 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.h @@ -86,6 +86,11 @@ public: tlm_utils::simple_target_socket tSocket; virtual void reportPower(); + + Dram(const Dram &) = delete; + Dram(Dram &&) = delete; + Dram &operator=(const Dram &) = delete; + Dram &operator=(Dram &&) = delete; ~Dram() override; }; diff --git a/src/simulator/simulator/Initiator.h b/src/simulator/simulator/Initiator.h index 4f6e0187..8cc14675 100644 --- a/src/simulator/simulator/Initiator.h +++ b/src/simulator/simulator/Initiator.h @@ -39,7 +39,14 @@ class Initiator { +protected: + Initiator(const Initiator &) = default; + Initiator(Initiator &&) = default; + Initiator &operator=(const Initiator &) = default; + Initiator &operator=(Initiator &&) = default; + public: + Initiator() = default; virtual ~Initiator() = default; virtual void bind(tlm_utils::multi_target_base<> &target) = 0; diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index f5dc99b5..52c760a1 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -45,7 +45,12 @@ class MemoryManager : public tlm::tlm_mm_interface { public: explicit MemoryManager(bool storageEnabled); + MemoryManager(const MemoryManager &) = delete; + MemoryManager(MemoryManager &&) = delete; + MemoryManager &operator=(const MemoryManager &) = delete; + MemoryManager &operator=(MemoryManager &&) = delete; ~MemoryManager() override; + tlm::tlm_generic_payload& allocate(unsigned dataLength); void free(tlm::tlm_generic_payload* payload) override; diff --git a/src/simulator/simulator/request/RequestProducer.h b/src/simulator/simulator/request/RequestProducer.h index 212f14c6..5c22ead1 100644 --- a/src/simulator/simulator/request/RequestProducer.h +++ b/src/simulator/simulator/request/RequestProducer.h @@ -39,7 +39,14 @@ class RequestProducer { +protected: + RequestProducer(const RequestProducer &) = default; + RequestProducer(RequestProducer &&) = default; + RequestProducer &operator=(const RequestProducer &) = default; + RequestProducer &operator=(RequestProducer &&) = default; + public: + RequestProducer() = default; virtual ~RequestProducer() = default; virtual Request nextRequest() = 0; diff --git a/src/util/DRAMSys/util/json.h b/src/util/DRAMSys/util/json.h index 5279c8f1..5d34a4b2 100644 --- a/src/util/DRAMSys/util/json.h +++ b/src/util/DRAMSys/util/json.h @@ -142,6 +142,8 @@ struct adl_serializer> { NLOHMANN_JSON_NAMESPACE_END +// NOLINTBEGIN(cppcoreguidelines-macro-usage) + #define EXTEND_JSON_TO(v1) DRAMSys::util::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); #define EXTEND_JSON_FROM(v1) DRAMSys::util::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); @@ -153,4 +155,6 @@ NLOHMANN_JSON_NAMESPACE_END NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \ } -#endif \ No newline at end of file +// NOLINTEND(cppcoreguidelines-macro-usage) + +#endif // DRAMSYS_UTIL_JSON_H From 3ce54b8faa6b9e1dc2d637df918c7e11cfc6441a Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 17 May 2023 12:02:35 +0200 Subject: [PATCH 10/16] Fix readability-misleading-indentation warnings --- .../DRAMSys/controller/BankMachine.cpp | 180 +++++++++--------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index fb74fe6d..cdcebf56 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -171,7 +171,7 @@ void BankMachineOpen::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -180,27 +180,27 @@ void BankMachineOpen::evaluate() { if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + } + else + { + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - nextCommand = Command::WR; - } - else // row miss - nextCommand = Command::PREPB; + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; + else + nextCommand = Command::WR; } + else // row miss + nextCommand = Command::PREPB; + } } } @@ -213,7 +213,7 @@ void BankMachineClosed::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -222,22 +222,22 @@ void BankMachineClosed::evaluate() { if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + } + else + { + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - nextCommand = Command::WRA; - } + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; + else + nextCommand = Command::WRA; + } } } @@ -250,7 +250,7 @@ void BankMachineOpenAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -259,39 +259,39 @@ void BankMachineOpenAdaptive::evaluate() { if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + } + else + { + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit + if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) && + !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { - if (scheduler.hasFurtherRequest(bank, currentPayload->get_command()) - && !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - nextCommand = Command::WRA; - } + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; else - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - nextCommand = Command::WR; - } + nextCommand = Command::WRA; + } + else + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; + else + nextCommand = Command::WR; } - else // row miss - nextCommand = Command::PREPB; } + else // row miss + nextCommand = Command::PREPB; + } } } @@ -305,7 +305,7 @@ void BankMachineClosedAdaptive::evaluate() if (!(sleeping || blocked)) { - tlm_generic_payload* newPayload = scheduler.getNextRequest(*this); + tlm_generic_payload *newPayload = scheduler.getNextRequest(*this); if (newPayload == nullptr) return; @@ -314,38 +314,38 @@ void BankMachineClosedAdaptive::evaluate() { if (ControllerExtension::getRow(*newPayload) == openRow) currentPayload = newPayload; - } - else - { - currentPayload = newPayload; - } + } + else + { + currentPayload = newPayload; + } - if (state == State::Precharged) // bank precharged - nextCommand = Command::ACT; - else if (state == State::Activated) + if (state == State::Precharged) // bank precharged + nextCommand = Command::ACT; + else if (state == State::Activated) + { + if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit { - if (ControllerExtension::getRow(*currentPayload) == openRow) // row hit + if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) { - if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command())) - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RD; - else - nextCommand = Command::WR; - } + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RD; else - { - assert(currentPayload->is_read() || currentPayload->is_write()); - if (currentPayload->is_read()) - nextCommand = Command::RDA; - else - nextCommand = Command::WRA; - } + nextCommand = Command::WR; + } + else + { + assert(currentPayload->is_read() || currentPayload->is_write()); + if (currentPayload->is_read()) + nextCommand = Command::RDA; + else + nextCommand = Command::WRA; } - else // row miss, can happen when RD/WR mode is switched - nextCommand = Command::PREPB; } + else // row miss, can happen when RD/WR mode is switched + nextCommand = Command::PREPB; + } } } From 55bbaf632df43ac3bfd223daec85ee3b14a0f419 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 19 May 2023 10:09:58 +0200 Subject: [PATCH 11/16] Fix incorrect copyright disclaimer in Cache --- src/simulator/simulator/Cache.cpp | 72 ++++++++++++++++++------- src/simulator/simulator/Cache.h | 2 +- src/simulator/simulator/MemoryManager.h | 1 + 3 files changed, 55 insertions(+), 20 deletions(-) diff --git a/src/simulator/simulator/Cache.cpp b/src/simulator/simulator/Cache.cpp index c40ce13c..325e929d 100644 --- a/src/simulator/simulator/Cache.cpp +++ b/src/simulator/simulator/Cache.cpp @@ -1,3 +1,39 @@ +/* + * Copyright (c) 2022, Technische Universität Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + * Derek Christ + */ + #include "Cache.h" #include "MemoryManager.h" @@ -368,29 +404,27 @@ Cache::CacheLine *Cache::evictLine(Cache::index_t index) // There are still hits in hitQueue to the oldest line -> do not evict it return nullptr; } - else + + if (oldestLine.valid && oldestLine.dirty) { - if (oldestLine.valid && oldestLine.dirty) - { - auto &wbTrans = memoryManager.allocate(lineSize); - wbTrans.acquire(); - wbTrans.set_address(encodeAddress(index, oldestLine.tag)); - wbTrans.set_write(); - wbTrans.set_data_length(lineSize); - wbTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); + auto &wbTrans = memoryManager.allocate(lineSize); + wbTrans.acquire(); + wbTrans.set_address(encodeAddress(index, oldestLine.tag)); + wbTrans.set_write(); + wbTrans.set_data_length(lineSize); + wbTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); - if (storageEnabled) - std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans.get_data_ptr()); + if (storageEnabled) + std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans.get_data_ptr()); - writeBuffer.emplace_back(index, oldestLine.tag, &wbTrans); - } - - oldestLine.allocated = false; - oldestLine.valid = false; - oldestLine.dirty = false; - - return &oldestLine; + writeBuffer.emplace_back(index, oldestLine.tag, &wbTrans); } + + oldestLine.allocated = false; + oldestLine.valid = false; + oldestLine.dirty = false; + + return &oldestLine; } /// Align address to cache line size diff --git a/src/simulator/simulator/Cache.h b/src/simulator/simulator/Cache.h index 3236d54f..978ff17f 100644 --- a/src/simulator/simulator/Cache.h +++ b/src/simulator/simulator/Cache.h @@ -30,7 +30,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: - * Christian Malek + * Lukas Steiner * Derek Christ */ diff --git a/src/simulator/simulator/MemoryManager.h b/src/simulator/simulator/MemoryManager.h index 52c760a1..7cbe33f1 100644 --- a/src/simulator/simulator/MemoryManager.h +++ b/src/simulator/simulator/MemoryManager.h @@ -32,6 +32,7 @@ * Authors: * Robert Gernhardt * Matthias Jung + * Derek Christ */ #ifndef MEMORYMANAGER_H From 9799748ed25d9873a4a495e2e7d28f61a7433604 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 22 May 2023 11:55:52 +0200 Subject: [PATCH 12/16] Disable readability-function-cognitive-complexity clang-tidy check --- .clang-tidy | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.clang-tidy b/.clang-tidy index 33ff78e5..3df71291 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -1,5 +1,5 @@ --- -Checks: 'clang-diagnostic-*,clang-analyzer-*,modernize-*,bugprone-*,concurrency-*,cppcoreguidelines-*,performance-*,portability-*,readability-*,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-identifier-length' +Checks: 'clang-diagnostic-*,clang-analyzer-*,modernize-*,bugprone-*,concurrency-*,cppcoreguidelines-*,performance-*,portability-*,readability-*,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-identifier-length,-readability-function-cognitive-complexity' WarningsAsErrors: '' HeaderFilterRegex: '' AnalyzeTemporaryDtors: false From 0073331948fc1eb25d19441c4e9e2bd452b20e4a Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Wed, 24 May 2023 11:52:56 +0200 Subject: [PATCH 13/16] Use left pointer alignment in .clang-format --- .clang-format | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) mode change 100644 => 100755 .clang-format diff --git a/.clang-format b/.clang-format old mode 100644 new mode 100755 index 1dd7cebc..42b338db --- a/.clang-format +++ b/.clang-format @@ -1,4 +1,4 @@ ---- +--- AccessModifierOffset: '-4' AllowShortFunctionsOnASingleLine: InlineOnly AllowShortIfStatementsOnASingleLine: Never @@ -8,5 +8,6 @@ BreakBeforeBraces: Allman ColumnLimit: '100' ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' IndentWidth: '4' +PointerAlignment: Left ... From 60e0c6794c1a866a64dce0afd8d4f4a951730961 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 5 Jun 2023 10:31:19 +0200 Subject: [PATCH 14/16] Format .clang-tidy and .clang-format --- .clang-format | 5 +---- .clang-tidy | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/.clang-format b/.clang-format index 42b338db..5b1db6ed 100755 --- a/.clang-format +++ b/.clang-format @@ -1,5 +1,4 @@ ---- -AccessModifierOffset: '-4' +AccessModifierOffset: '-4' AllowShortFunctionsOnASingleLine: InlineOnly AllowShortIfStatementsOnASingleLine: Never BinPackArguments: 'false' @@ -9,5 +8,3 @@ ColumnLimit: '100' ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' IndentWidth: '4' PointerAlignment: Left - -... diff --git a/.clang-tidy b/.clang-tidy index 3df71291..15cccef3 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -1,7 +1,18 @@ ---- -Checks: 'clang-diagnostic-*,clang-analyzer-*,modernize-*,bugprone-*,concurrency-*,cppcoreguidelines-*,performance-*,portability-*,readability-*,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-identifier-length,-readability-function-cognitive-complexity' +Checks: > + clang-diagnostic-*, + clang-analyzer-*, + modernize-*, + bugprone-*, + concurrency-*, + cppcoreguidelines-*, + performance-*, + portability-*, + readability-*, + -modernize-use-trailing-return-type, + -readability-braces-around-statements, + -readability-identifier-length, + -readability-function-cognitive-complexity WarningsAsErrors: '' HeaderFilterRegex: '' AnalyzeTemporaryDtors: false FormatStyle: file -... From 1208d3e79919ae1ebc5632ae3035b68100db0954 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 9 Jun 2023 11:30:11 +0200 Subject: [PATCH 15/16] Add BreakConstructorInitializers: AfterColon to .clang-format --- .clang-format | 1 + 1 file changed, 1 insertion(+) diff --git a/.clang-format b/.clang-format index 5b1db6ed..afdb4719 100755 --- a/.clang-format +++ b/.clang-format @@ -4,6 +4,7 @@ AllowShortIfStatementsOnASingleLine: Never BinPackArguments: 'false' BinPackParameters: 'false' BreakBeforeBraces: Allman +BreakConstructorInitializers: AfterColon ColumnLimit: '100' ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' IndentWidth: '4' From f1cfb80337d0f4703ced4aec37bd4ad0ae0fd53a Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 21 Aug 2023 10:10:49 +0200 Subject: [PATCH 16/16] Minor readability fixes --- .../DRAMSys/controller/Controller.cpp | 4 ++-- .../controller/scheduler/SchedulerFrFcfs.cpp | 18 +++++++------- .../scheduler/SchedulerGrpFrFcfs.cpp | 24 +++++++++---------- .../scheduler/SchedulerGrpFrFcfsWm.cpp | 24 +++++++++---------- 4 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 7a4206b6..74ff6042 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -293,7 +293,7 @@ void Controller::controllerMethod() readyCommands.emplace_back(commandTuple); // (4.3) Check for bank commands (PREPB, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachinesOnRank[rank]) + for (auto* it : bankMachinesOnRank[rank]) { commandTuple = it->getNextCommand(); if (std::get(commandTuple) != Command::NOP) @@ -322,7 +322,7 @@ void Controller::controllerMethod() if (command.isRankCommand()) { - for (auto it : bankMachinesOnRank[rank]) + for (auto* it : bankMachinesOnRank[rank]) it->update(command); } else if (command.isGroupCommand()) diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index f27a07fc..dfdd566e 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -60,19 +60,19 @@ bool SchedulerFrFcfs::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerFrFcfs::storeRequest(tlm_generic_payload& trans) +void SchedulerFrFcfs::storeRequest(tlm_generic_payload& payload) { - buffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + buffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); } -void SchedulerFrFcfs::removeRequest(tlm_generic_payload& trans) +void SchedulerFrFcfs::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + Bank bank = ControllerExtension::getBank(payload); for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - if (*it == &trans) + if (*it == &payload) { buffer[bank].erase(it); break; @@ -89,7 +89,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach { // Search for row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : buffer[bank]) + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it; @@ -104,7 +104,7 @@ tlm_generic_payload* SchedulerFrFcfs::getNextRequest(const BankMachine& bankMach bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row, [[maybe_unused]] tlm_command command) const { unsigned rowHitCounter = 0; - for (auto it : buffer[bank]) + for (auto* it : buffer[bank]) { if (ControllerExtension::getRow(*it) == row) { diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index 49c2d364..0fb5091d 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -63,25 +63,25 @@ bool SchedulerGrpFrFcfs::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfs::storeRequest(tlm_generic_payload& payload) { - if (trans.is_read()) - readBuffer[ControllerExtension::getBank(trans)].push_back(&trans); + if (payload.is_read()) + readBuffer[ControllerExtension::getBank(payload)].push_back(&payload); else - writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); } -void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfs::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - lastCommand = trans.get_command(); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + lastCommand = payload.get_command(); + Bank bank = ControllerExtension::getBank(payload); - if (trans.is_read()) - readBuffer[bank].remove(&trans); + if (payload.is_read()) + readBuffer[bank].remove(&payload); else - writeBuffer[bank].remove(&trans); + writeBuffer[bank].remove(&payload); } tlm_generic_payload* SchedulerGrpFrFcfs::getNextRequest(const BankMachine& bankMachine) const diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 61145a4f..1957d020 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -67,25 +67,25 @@ bool SchedulerGrpFrFcfsWm::hasBufferSpace() const return bufferCounter->hasBufferSpace(); } -void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfsWm::storeRequest(tlm_generic_payload& payload) { - if (trans.is_read()) - readBuffer[ControllerExtension::getBank(trans)].push_back(&trans); + if (payload.is_read()) + readBuffer[ControllerExtension::getBank(payload)].push_back(&payload); else - writeBuffer[ControllerExtension::getBank(trans)].push_back(&trans); - bufferCounter->storeRequest(trans); + writeBuffer[ControllerExtension::getBank(payload)].push_back(&payload); + bufferCounter->storeRequest(payload); evaluateWriteMode(); } -void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& trans) +void SchedulerGrpFrFcfsWm::removeRequest(tlm_generic_payload& payload) { - bufferCounter->removeRequest(trans); - Bank bank = ControllerExtension::getBank(trans); + bufferCounter->removeRequest(payload); + Bank bank = ControllerExtension::getBank(payload); - if (trans.is_read()) - readBuffer[bank].remove(&trans); + if (payload.is_read()) + readBuffer[bank].remove(&payload); else - writeBuffer[bank].remove(&trans); + writeBuffer[bank].remove(&payload); evaluateWriteMode(); } @@ -120,7 +120,7 @@ tlm_generic_payload* SchedulerGrpFrFcfsWm::getNextRequest(const BankMachine& ban { // Search for write row hit Row openRow = bankMachine.getOpenRow(); - for (auto it : writeBuffer[bank]) + for (auto* it : writeBuffer[bank]) { if (ControllerExtension::getRow(*it) == openRow) return it;