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Implement Partial Write for DDR5

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This commit is contained in:
Derek Christ
2023-08-15 11:57:28 +02:00
parent 40dbc518b6
commit c5f1320399
11 changed files with 27 additions and 25 deletions
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14
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
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@@ -133,7 +133,9 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
commandLengthInCycles[Command::RD] = 2;
commandLengthInCycles[Command::RDA] = 2;
commandLengthInCycles[Command::WR] = 2;
commandLengthInCycles[Command::MWR] = 2;
commandLengthInCycles[Command::WRA] = 2;
commandLengthInCycles[Command::MWRA] = 2;
}
else if (cmdMode == 2)
{
@@ -144,7 +146,9 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
commandLengthInCycles[Command::RD] = 4;
commandLengthInCycles[Command::RDA] = 4;
commandLengthInCycles[Command::WR] = 4;
commandLengthInCycles[Command::MWR] = 4;
commandLengthInCycles[Command::WRA] = 4;
commandLengthInCycles[Command::MWRA] = 4;
commandLengthInCycles[Command::REFAB] = 2;
commandLengthInCycles[Command::RFMAB] = 2;
commandLengthInCycles[Command::REFSB] = 2;
@@ -279,14 +283,12 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
}
}
bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
// auto burstLength = ControllerExtension::getBurstLength(payload);
auto burstLength = ControllerExtension::getBurstLength(payload);
// if (burstLength == 16 && bitWidth == 4)
// return true;
// assert(false); // TODO
if (burstLength == 16 && bitWidth == 4)
return true;
return payload.get_byte_enable_ptr() != nullptr;
}

2
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
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@@ -129,7 +129,7 @@ public:
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

4
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
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@@ -441,7 +441,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
}
}
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
{
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank];
if (lastCommandStart != scMaxTime)
@@ -517,7 +517,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
}
}
if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW
if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW
{
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup];
if (lastCommandStart != scMaxTime)

2
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -248,7 +248,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
}
}
bool MemSpecLPDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
// assert(false); // TODO
return payload.get_byte_enable_ptr() != nullptr;

2
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
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@@ -120,7 +120,7 @@ public:
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
private:
unsigned per2BankOffset;

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -148,7 +148,7 @@ bool MemSpec::hasRasAndCasBus() const
return false;
}
bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -102,7 +102,7 @@ public:
virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const;
sc_core::sc_time getCommandLength(Command) const;
double getCommandLengthInCycles(Command) const;

16
src/libdramsys/DRAMSys/controller/BankMachine.cpp
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@@ -70,11 +70,11 @@ void BankMachine::update(Command command)
state = State::Precharged;
keepTrans = false;
break;
case Command::RD: case Command::WR:
case Command::RD: case Command::WR: case Command::MWR:
currentPayload = nullptr;
keepTrans = false;
break;
case Command::RDA: case Command::WRA:
case Command::RDA: case Command::WRA: case Command::MWRA:
state = State::Precharged;
currentPayload = nullptr;
keepTrans = false;
@@ -201,7 +201,7 @@ void BankMachineOpen::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else // row miss
@@ -247,7 +247,7 @@ void BankMachineClosed::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}
@@ -295,7 +295,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
else
@@ -305,7 +305,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
}
@@ -357,7 +357,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else
@@ -367,7 +367,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp
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@@ -181,7 +181,7 @@ void RefreshManagerAllBank::update(Command command)
case Command::ACT:
activatedBanks++;
break;
case Command::PREPB: case Command::RDA: case Command::WRA:
case Command::PREPB: case Command::RDA: case Command::WRA: case Command::MWRA:
activatedBanks--;
break;
case Command::PREAB:

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tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb LFS
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tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb LFS
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