From c5f1320399c1e2c2f2d7bffac391dfb280d17142 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 15 Aug 2023 11:57:28 +0200 Subject: [PATCH] Implement Partial Write for DDR5 --- .../configuration/memspec/MemSpecDDR5.cpp | 14 ++++++++------ .../DRAMSys/configuration/memspec/MemSpecDDR5.h | 2 +- .../DRAMSys/controller/checker/CheckerDDR5.cpp | 4 ++-- .../configuration/memspec/MemSpecLPDDR5.cpp | 2 +- .../configuration/memspec/MemSpecLPDDR5.h | 2 +- .../DRAMSys/configuration/memspec/MemSpec.cpp | 2 +- .../DRAMSys/configuration/memspec/MemSpec.h | 2 +- .../DRAMSys/controller/BankMachine.cpp | 16 ++++++++-------- .../controller/refresh/RefreshManagerAllBank.cpp | 2 +- .../expected/DRAMSys_ddr5-example_ddr5_ch0.tdb | 4 ++-- .../expected/DRAMSys_ddr5-example_ddr5_ch1.tdb | 2 +- 11 files changed, 27 insertions(+), 25 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index ecd07d8a..605f0176 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -133,7 +133,9 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) commandLengthInCycles[Command::RD] = 2; commandLengthInCycles[Command::RDA] = 2; commandLengthInCycles[Command::WR] = 2; + commandLengthInCycles[Command::MWR] = 2; commandLengthInCycles[Command::WRA] = 2; + commandLengthInCycles[Command::MWRA] = 2; } else if (cmdMode == 2) { @@ -144,7 +146,9 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) commandLengthInCycles[Command::RD] = 4; commandLengthInCycles[Command::RDA] = 4; commandLengthInCycles[Command::WR] = 4; + commandLengthInCycles[Command::MWR] = 4; commandLengthInCycles[Command::WRA] = 4; + commandLengthInCycles[Command::MWRA] = 4; commandLengthInCycles[Command::REFAB] = 2; commandLengthInCycles[Command::RFMAB] = 2; commandLengthInCycles[Command::REFSB] = 2; @@ -279,14 +283,12 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen } } -bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const +bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { - // auto burstLength = ControllerExtension::getBurstLength(payload); + auto burstLength = ControllerExtension::getBurstLength(payload); - // if (burstLength == 16 && bitWidth == 4) - // return true; - - // assert(false); // TODO + if (burstLength == 16 && bitWidth == 4) + return true; return payload.get_byte_enable_ptr() != nullptr; } diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index dacc5ef1..e09e5c44 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -129,7 +129,7 @@ public: sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; - bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override; + bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index 153a39a9..b2400ef2 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -441,7 +441,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank]; if (lastCommandStart != scMaxTime) @@ -517,7 +517,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic } } - if (burstLength == 16 && memSpec->bitWidth == 4) // second WR requires RMW + if (memSpec->requiresMaskedWrite(payload)) // second WR requires RMW { lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup]; if (lastCommandStart != scMaxTime) diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 154b78d9..2ccee628 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -248,7 +248,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g } } -bool MemSpecLPDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const +bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { // assert(false); // TODO return payload.get_byte_enable_ptr() != nullptr; diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h index 594ba768..570ae949 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h @@ -120,7 +120,7 @@ public: sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; - bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override; + bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index 7fc5b70d..dd512c81 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -148,7 +148,7 @@ bool MemSpec::hasRasAndCasBus() const return false; } -bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const +bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { return payload.get_byte_enable_ptr() != nullptr; } diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 7b28e7ac..c2c91fff 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -102,7 +102,7 @@ public: virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const; + virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const; sc_core::sc_time getCommandLength(Command) const; double getCommandLengthInCycles(Command) const; diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index 3f04671f..85ec6098 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -70,11 +70,11 @@ void BankMachine::update(Command command) state = State::Precharged; keepTrans = false; break; - case Command::RD: case Command::WR: + case Command::RD: case Command::WR: case Command::MWR: currentPayload = nullptr; keepTrans = false; break; - case Command::RDA: case Command::WRA: + case Command::RDA: case Command::WRA: case Command::MWRA: state = State::Precharged; currentPayload = nullptr; keepTrans = false; @@ -201,7 +201,7 @@ void BankMachineOpen::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } else // row miss @@ -247,7 +247,7 @@ void BankMachineClosed::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } } @@ -295,7 +295,7 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } else @@ -305,7 +305,7 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } } @@ -357,7 +357,7 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } else @@ -367,7 +367,7 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } } diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index 7a2a22f3..b35c9bdf 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -181,7 +181,7 @@ void RefreshManagerAllBank::update(Command command) case Command::ACT: activatedBanks++; break; - case Command::PREPB: case Command::RDA: case Command::WRA: + case Command::PREPB: case Command::RDA: case Command::WRA: case Command::MWRA: activatedBanks--; break; case Command::PREAB: diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb index f8d7441f..d7c96b81 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5e0c71bd6f04a8e5547ef4207740b00b5ca68e02c6a7b99d998365809b54fc9d -size 6041600 +oid sha256:0e8a22954bf100e69ceb7d9454d61a6c575c67f087b84658d05d5b394d94b9c6 +size 6045696 diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb index 7ebed659..091bea04 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:efd6b710929d4d02b83950b5e4bc2b5fed39c66a6d6d850802902b8db3f8c17d +oid sha256:a77f157b1929b8e4f5302e68b06ef468cbb2edf32e6c57579dfceb777c6d528e size 94208