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Do not allow masked write in default case.

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This commit is contained in:
Lukas Steiner
2023-08-23 11:41:58 +02:00
parent 8c248e8e23
commit 0f824e8b92
26 changed files with 101 additions and 55 deletions
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2
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
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@@ -283,7 +283,7 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
}
}
bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
auto burstLength = ControllerExtension::getBurstLength(payload);

16
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
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@@ -119,17 +119,17 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalSB() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
[[nodiscard]] unsigned getRAADEC() const override;
[[nodiscard]] unsigned getRAAIMT() const override;
[[nodiscard]] unsigned getRAAMMT() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

12
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
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@@ -197,16 +197,4 @@ unsigned MemSpecHBM3::getRAAMMT() const
return RAAMMT;
}
bool MemSpecHBM3::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
{
bool maskedWrite = payload.get_byte_enable_ptr() != nullptr;
if (maskedWrite)
{
SC_REPORT_FATAL("MemSpecHBM3", "HBM3 does not support masked writes!");
}
return maskedWrite;
}
} // namespace DRAMSys

18
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
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@@ -89,19 +89,17 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
[[nodiscard]] unsigned getRAADEC() const override;
[[nodiscard]] unsigned getRAAIMT() const override;
[[nodiscard]] unsigned getRAAMMT() const override;
bool hasRasAndCasBus() const override;
[[nodiscard]] bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

5
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -248,4 +248,9 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
}
}
bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

14
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
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@@ -111,14 +111,16 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalP2B() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
unsigned getPer2BankOffset() const override;
[[nodiscard]] unsigned getPer2BankOffset() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
private:
unsigned per2BankOffset;

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -148,9 +148,13 @@ bool MemSpec::hasRasAndCasBus() const
return false;
}
bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
if (payload.get_byte_enable_ptr() == nullptr)
return false;
SC_REPORT_FATAL("MemSpec", "Standard does not support masked writes!");
throw;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -103,7 +103,7 @@ public:
[[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
[[nodiscard]] virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const;
[[nodiscard]] sc_core::sc_time getCommandLength(Command command) const;
[[nodiscard]] double getCommandLengthInCycles(Command command) const;

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
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@@ -168,4 +168,9 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unuse
throw;
}
bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h
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@@ -97,6 +97,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
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@@ -186,4 +186,9 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unuse
throw;
}
bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
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@@ -104,6 +104,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
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@@ -145,10 +145,10 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
if (command == Command::RDA)
return tRTP + tRP;
if (command == Command::WR || command == Command::MWR)
if (command == Command::WR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA)
return tWL + burstDuration + tWR + tRP;
if (command == Command::REFAB)
@@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unus
if (command == Command::RD || command == Command::RDA)
return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
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@@ -145,10 +145,10 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
if (command == Command::RDA)
return tRTP + tRP;
if (command == Command::WR || command == Command::MWR)
if (command == Command::WR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA)
return tWL + burstDuration + tWR + tRP;
if (command == Command::REFAB)
@@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unu
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
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@@ -158,10 +158,10 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
if (command == Command::RDA)
return tRTP + tRP;
if (command == Command::WR || command == Command::MWR)
if (command == Command::WR)
return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
if (command == Command::WRA || command == Command::MWRA)
if (command == Command::WRA)
return tWL + burstDuration + tWR + tRP;
if (command == Command::REFAB)
@@ -180,7 +180,7 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unus
if (command == Command::RD || command == Command::RDA)
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
if (command == Command::WR || command == Command::WRA)
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
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@@ -175,4 +175,9 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unuse
throw;
}
bool MemSpecHBM2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h
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@@ -92,6 +92,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -181,4 +181,9 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unu
throw;
}
bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
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@@ -92,6 +92,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
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@@ -141,4 +141,9 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_un
throw;
}
bool MemSpecSTTMRAM::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h
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@@ -80,6 +80,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
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@@ -173,4 +173,9 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unu
throw;
}
bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h
View File

@@ -102,6 +102,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

5
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -163,4 +163,9 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_un
throw;
}
bool MemSpecWideIO2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h
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@@ -84,6 +84,8 @@ public:
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

12
src/libdramsys/DRAMSys/controller/BankMachine.cpp
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@@ -201,7 +201,7 @@ void BankMachineOpen::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else // row miss
@@ -243,7 +243,7 @@ void BankMachineClosed::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}
@@ -287,7 +287,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
else
@@ -297,7 +297,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
}
@@ -345,7 +345,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else
@@ -355,7 +355,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}