From 0f824e8b92810eb647ac1b440428bc6f1776b16c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 23 Aug 2023 11:41:58 +0200 Subject: [PATCH] Do not allow masked write in default case. --- .../configuration/memspec/MemSpecDDR5.cpp | 2 +- .../configuration/memspec/MemSpecDDR5.h | 16 ++++++++-------- .../configuration/memspec/MemSpecHBM3.cpp | 12 ------------ .../configuration/memspec/MemSpecHBM3.h | 18 ++++++++---------- .../configuration/memspec/MemSpecLPDDR5.cpp | 5 +++++ .../configuration/memspec/MemSpecLPDDR5.h | 14 ++++++++------ .../DRAMSys/configuration/memspec/MemSpec.cpp | 8 ++++++-- .../DRAMSys/configuration/memspec/MemSpec.h | 2 +- .../configuration/memspec/MemSpecDDR3.cpp | 5 +++++ .../configuration/memspec/MemSpecDDR3.h | 2 ++ .../configuration/memspec/MemSpecDDR4.cpp | 5 +++++ .../configuration/memspec/MemSpecDDR4.h | 2 ++ .../configuration/memspec/MemSpecGDDR5.cpp | 6 +++--- .../configuration/memspec/MemSpecGDDR5X.cpp | 6 +++--- .../configuration/memspec/MemSpecGDDR6.cpp | 6 +++--- .../configuration/memspec/MemSpecHBM2.cpp | 5 +++++ .../configuration/memspec/MemSpecHBM2.h | 2 ++ .../configuration/memspec/MemSpecLPDDR4.cpp | 5 +++++ .../configuration/memspec/MemSpecLPDDR4.h | 2 ++ .../configuration/memspec/MemSpecSTTMRAM.cpp | 5 +++++ .../configuration/memspec/MemSpecSTTMRAM.h | 2 ++ .../configuration/memspec/MemSpecWideIO.cpp | 5 +++++ .../configuration/memspec/MemSpecWideIO.h | 2 ++ .../configuration/memspec/MemSpecWideIO2.cpp | 5 +++++ .../configuration/memspec/MemSpecWideIO2.h | 2 ++ .../DRAMSys/controller/BankMachine.cpp | 12 ++++++------ 26 files changed, 101 insertions(+), 55 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index 785b790c..605f0176 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -283,7 +283,7 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen } } -bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const +bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { auto burstLength = ControllerExtension::getBurstLength(payload); diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index dacc5ef1..d696d3d7 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -119,17 +119,17 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalSB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalSB() const override; - unsigned getRAADEC() const override; - unsigned getRAAIMT() const override; - unsigned getRAAMMT() const override; + [[nodiscard]] unsigned getRAADEC() const override; + [[nodiscard]] unsigned getRAAIMT() const override; + [[nodiscard]] unsigned getRAAMMT() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; - bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp index 8318e1f4..b251ee72 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp @@ -197,16 +197,4 @@ unsigned MemSpecHBM3::getRAAMMT() const return RAAMMT; } -bool MemSpecHBM3::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const -{ - bool maskedWrite = payload.get_byte_enable_ptr() != nullptr; - - if (maskedWrite) - { - SC_REPORT_FATAL("MemSpecHBM3", "HBM3 does not support masked writes!"); - } - - return maskedWrite; -} - } // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h index 852ac762..c5c65042 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h @@ -89,19 +89,17 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - unsigned getRAADEC() const override; - unsigned getRAAIMT() const override; - unsigned getRAAMMT() const override; + [[nodiscard]] unsigned getRAADEC() const override; + [[nodiscard]] unsigned getRAAIMT() const override; + [[nodiscard]] unsigned getRAAMMT() const override; - bool hasRasAndCasBus() const override; + [[nodiscard]] bool hasRasAndCasBus() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; - - bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 6793d0f9..9d175a72 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -248,4 +248,9 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g } } +bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h index 5091bc98..a66278d1 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h @@ -111,14 +111,16 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getRefreshIntervalP2B() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override; - unsigned getPer2BankOffset() const override; + [[nodiscard]] unsigned getPer2BankOffset() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index f02db58b..420e63c9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -148,9 +148,13 @@ bool MemSpec::hasRasAndCasBus() const return false; } -bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const +bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { - return payload.get_byte_enable_ptr() != nullptr; + if (payload.get_byte_enable_ptr() == nullptr) + return false; + + SC_REPORT_FATAL("MemSpec", "Standard does not support masked writes!"); + throw; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index d87c0841..e97d2e2f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -103,7 +103,7 @@ public: [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - [[nodiscard]] virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const; + [[nodiscard]] virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const; [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const; [[nodiscard]] double getCommandLengthInCycles(Command command) const; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 61c3a347..472997f4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -168,4 +168,9 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unuse throw; } +bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index f903de1d..0bcc7de3 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -97,6 +97,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index a99844be..0f109964 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -186,4 +186,9 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unuse throw; } +bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 1cf895d8..773b2e26 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -104,6 +104,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 18952687..63a6b5e7 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -145,10 +145,10 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa if (command == Command::RDA) return tRTP + tRP; - if (command == Command::WR || command == Command::MWR) + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - if (command == Command::WRA || command == Command::MWRA) + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; if (command == Command::REFAB) @@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unus if (command == Command::RD || command == Command::RDA) return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index fa64ee7e..f536f8b9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -145,10 +145,10 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo if (command == Command::RDA) return tRTP + tRP; - if (command == Command::WR || command == Command::MWR) + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - if (command == Command::WRA || command == Command::MWRA) + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; if (command == Command::REFAB) @@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unu if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 9339abe4..23fae0c4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -158,10 +158,10 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa if (command == Command::RDA) return tRTP + tRP; - if (command == Command::WR || command == Command::MWR) + if (command == Command::WR) return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration; - if (command == Command::WRA || command == Command::MWRA) + if (command == Command::WRA) return tWL + burstDuration + tWR + tRP; if (command == Command::REFAB) @@ -180,7 +180,7 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unus if (command == Command::RD || command == Command::RDA) return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; - if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA) + if (command == Command::WR || command == Command::WRA) return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index e76d4d1f..2bc529c1 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -175,4 +175,9 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unuse throw; } +bool MemSpecHBM2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index b4c681c8..38022b33 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -92,6 +92,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index 9c5597ff..251ab31c 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -181,4 +181,9 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unu throw; } +bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 931300f8..2a0982a8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -92,6 +92,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index 0819d78f..4a46edcd 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -141,4 +141,9 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_un throw; } +bool MemSpecSTTMRAM::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index dd2e09d9..9de3a320 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -80,6 +80,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index f0fcb503..796c63e2 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -173,4 +173,9 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unu throw; } +bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index 5f62b761..4b76fa2f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -102,6 +102,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index 55cc06db..560ae295 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -163,4 +163,9 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_un throw; } +bool MemSpecWideIO2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const +{ + return payload.get_byte_enable_ptr() != nullptr; +} + } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 3b418b62..e6a62637 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -84,6 +84,8 @@ public: [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + + [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index e6ba0643..84ffe90b 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -201,7 +201,7 @@ void BankMachineOpen::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } else // row miss @@ -243,7 +243,7 @@ void BankMachineClosed::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } } @@ -287,7 +287,7 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } else @@ -297,7 +297,7 @@ void BankMachineOpenAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } } @@ -345,7 +345,7 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RD; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR; } } else @@ -355,7 +355,7 @@ void BankMachineClosedAdaptive::evaluate() nextCommand = Command::RDA; else { - nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA; + nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA; } } }