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Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files

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This commit is contained in:
Derek Christ
2023-11-14 14:57:25 +01:00
parent 1050019db6
commit 6645a9ed54
40 changed files with 338 additions and 1877 deletions
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51
extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp
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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2020, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramDDR5.h"
using namespace sc_core;
namespace DRAMSys
{
DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramDDR5", "DRAMPower does not support DDR5");
#endif
}
} // namespace DRAMSys

55
extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2020, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMDDR5_H
#define DRAMDDR5_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramDDR5 : public Dram
{
public:
DramDDR5(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramDDR5);
};
} // namespace DRAMSys
#endif // DRAMDDR5_H

54
extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp
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@@ -1,54 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramHBM3.h"
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
using namespace sc_core;
namespace DRAMSys
{
DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3");
#endif
}
} // namespace DRAMSys

55
extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMHBM3_H
#define DRAMHBM3_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramHBM3 : public Dram
{
public:
DramHBM3(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramHBM3);
};
} // namespace DRAMSys
#endif // DRAMHBM3_H

54
extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp
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@@ -1,54 +0,0 @@
/*
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramLPDDR5.h"
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
using namespace sc_core;
namespace DRAMSys
{
DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramLPDDR5", "DRAMPower does not support LPDDR5");
#endif
}
} // namespace DRAMSys

55
extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMLPDDR5_H
#define DRAMLPDDR5_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramLPDDR5 : public Dram
{
public:
DramLPDDR5(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramLPDDR5);
};
} // namespace DRAMSys
#endif // DRAMLPDDR5_H

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -177,4 +177,12 @@ bool MemSpec::allBytesEnabled(const tlm::tlm_generic_payload& trans)
return true;
}
#ifdef DRAMPOWER
DRAMPower::MemorySpecification MemSpec::toDramPowerMemSpec() const
{
SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard");
return {};
}
#endif
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -48,6 +48,10 @@
#include <tlm>
#include <vector>
#ifdef DRAMPOWER
#include <LibDRAMPower.h>
#endif
namespace DRAMSys
{
@@ -122,6 +126,10 @@ public:
[[nodiscard]] double getCommandLengthInCycles(Command command) const;
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
#ifdef DRAMPOWER
[[nodiscard]] virtual DRAMPower::MemorySpecification toDramPowerMemSpec() const;
#endif
protected:
MemSpec(const DRAMSys::Config::MemSpec& memSpec,
MemoryType memoryType,

93
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
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@@ -182,4 +182,97 @@ bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
DRAMPower::MemorySpecification MemSpecDDR3::toDramPowerMemSpec() const
{
DRAMPower::MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = defaultBurstLength;
memArchSpec.dataRate = dataRate;
memArchSpec.nbrOfRows = rowsPerBank;
memArchSpec.nbrOfBanks = banksPerChannel;
memArchSpec.nbrOfColumns = columnsPerRow;
memArchSpec.nbrOfRanks = ranksPerChannel;
memArchSpec.width = bitWidth;
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = false;
memArchSpec.dll = true;
DRAMPower::MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = tFAW / tCK;
// FIXME: memTimingSpec.RASB = tRAS / tCK;
// FIXME: memTimingSpec.RCB = tRC / tCK;
// FIXME: memTimingSpec.RPB = tRP / tCK;
// FIXME: memTimingSpec.RRDB = tRRD / tCK;
// FIXME: memTimingSpec.RRDB_L = tRRD / tCK;
// FIXME: memTimingSpec.RRDB_S = tRRD / tCK;
memTimingSpec.AL = tAL / tCK;
memTimingSpec.CCD = tCCD / tCK;
memTimingSpec.CCD_L = tCCD / tCK;
memTimingSpec.CCD_S = tCCD / tCK;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tFAW / tCK;
memTimingSpec.RAS = tRAS / tCK;
memTimingSpec.RC = tRC / tCK;
memTimingSpec.RCD = tRCD / tCK;
memTimingSpec.REFI = tREFI / tCK;
memTimingSpec.RFC = tRFC / tCK;
memTimingSpec.RL = tRL / tCK;
memTimingSpec.RP = tRP / tCK;
memTimingSpec.RRD = tRRD / tCK;
memTimingSpec.RRD_L = tRRD / tCK;
memTimingSpec.RRD_S = tRRD / tCK;
memTimingSpec.RTP = tRTP / tCK;
memTimingSpec.TAW = tFAW / tCK;
memTimingSpec.WL = tWL / tCK;
memTimingSpec.WR = tWR / tCK;
memTimingSpec.WTR = tWTR / tCK;
memTimingSpec.WTR_L = tWTR / tCK;
memTimingSpec.WTR_S = tWTR / tCK;
memTimingSpec.XP = tXP / tCK;
memTimingSpec.XPDLL = tXPDLL / tCK;
memTimingSpec.XS = tXS / tCK;
memTimingSpec.XSDLL = tXSDLL / tCK;
DRAMPower::MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = iDD0;
memPowerSpec.idd02 = 0;
memPowerSpec.idd2p0 = iDD2P0;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = iDD2P1;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = iDD2N;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = iDD3P0;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = iDD3P1;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = iDD3N;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = iDD4R;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = iDD4W;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = iDD5;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = iDD6;
memPowerSpec.idd62 = 0;
memPowerSpec.vdd = vDD;
memPowerSpec.vdd2 = 0;
DRAMPower::MemorySpecification powerSpec;
powerSpec.id = memoryId;
powerSpec.memoryType = DRAMPower::MemoryType::DDR3;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
return powerSpec;
}
#endif
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h
View File

@@ -102,6 +102,10 @@ public:
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
#endif
};
} // namespace DRAMSys

93
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -202,4 +202,97 @@ bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
DRAMPower::MemorySpecification MemSpecDDR4::toDramPowerMemSpec() const
{
DRAMPower::MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = defaultBurstLength;
memArchSpec.dataRate = dataRate;
memArchSpec.nbrOfRows = rowsPerBank;
memArchSpec.nbrOfBanks = banksPerChannel;
memArchSpec.nbrOfColumns = columnsPerRow;
memArchSpec.nbrOfRanks = ranksPerChannel;
memArchSpec.width = bitWidth;
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = true;
DRAMPower::MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = tFAW / tCK;
// FIXME: memTimingSpec.RASB = tRAS / tCK;
// FIXME: memTimingSpec.RCB = tRC / tCK;
// FIXME: memTimingSpec.RPB = tRP / tCK;
// FIXME: memTimingSpec.RRDB = tRRD_S / tCK;
// FIXME: memTimingSpec.RRDB_L = tRRD_L / tCK;
// FIXME: memTimingSpec.RRDB_S = tRRD_S / tCK;
memTimingSpec.AL = tAL / tCK;
memTimingSpec.CCD = tCCD_S / tCK;
memTimingSpec.CCD_L = tCCD_L / tCK;
memTimingSpec.CCD_S = tCCD_S / tCK;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tFAW / tCK;
memTimingSpec.RAS = tRAS / tCK;
memTimingSpec.RC = tRC / tCK;
memTimingSpec.RCD = tRCD / tCK;
memTimingSpec.REFI = tREFI / tCK;
memTimingSpec.RFC = tRFC / tCK;
memTimingSpec.RL = tRL / tCK;
memTimingSpec.RP = tRP / tCK;
memTimingSpec.RRD = tRRD_S / tCK;
memTimingSpec.RRD_L = tRRD_L / tCK;
memTimingSpec.RRD_S = tRRD_S / tCK;
memTimingSpec.RTP = tRTP / tCK;
memTimingSpec.TAW = tFAW / tCK;
memTimingSpec.WL = tWL / tCK;
memTimingSpec.WR = tWR / tCK;
memTimingSpec.WTR = tWTR_S / tCK;
memTimingSpec.WTR_L = tWTR_L / tCK;
memTimingSpec.WTR_S = tWTR_S / tCK;
memTimingSpec.XP = tXP / tCK;
memTimingSpec.XPDLL = tXPDLL / tCK;
memTimingSpec.XS = tXS / tCK;
memTimingSpec.XSDLL = tXSDLL / tCK;
DRAMPower::MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = iDD0;
memPowerSpec.idd02 = iDD02;
memPowerSpec.idd2p0 = iDD2P0;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = iDD2P1;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = iDD2N;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = iDD3P0;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = iDD3P1;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = iDD3N;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = iDD4R;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = iDD4W;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = iDD5;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = iDD6;
memPowerSpec.idd62 = iDD62;
memPowerSpec.vdd = vDD;
memPowerSpec.vdd2 = vDD2;
DRAMPower::MemorySpecification powerSpec;
powerSpec.id = memoryId;
powerSpec.memoryType = DRAMPower::MemoryType::DDR4;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
return powerSpec;
}
#endif
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
View File

@@ -109,6 +109,10 @@ public:
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
#endif
};
} // namespace DRAMSys

93
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -197,4 +197,97 @@ bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload)
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
DRAMPower::MemorySpecification MemSpecWideIO::toDramPowerMemSpec() const
{
DRAMPower::MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = defaultBurstLength;
memArchSpec.dataRate = dataRate;
memArchSpec.nbrOfRows = rowsPerBank;
memArchSpec.nbrOfBanks = banksPerChannel;
memArchSpec.nbrOfColumns = columnsPerRow;
memArchSpec.nbrOfRanks = ranksPerChannel;
memArchSpec.width = bitWidth;
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = false;
DRAMPower::MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = tTAW / tCK;
// FIXME: memTimingSpec.RASB = tRAS / tCK;
// FIXME: memTimingSpec.RCB = tRC / tCK;
// FIXME: memTimingSpec.RPB = tRP / tCK;
// FIXME: memTimingSpec.RRDB = tRRD / tCK;
// FIXME: memTimingSpec.RRDB_L = tRRD / tCK;
// FIXME: memTimingSpec.RRDB_S = tRRD / tCK;
memTimingSpec.AL = 0;
memTimingSpec.CCD = defaultBurstLength;
memTimingSpec.CCD_L = defaultBurstLength;
memTimingSpec.CCD_S = defaultBurstLength;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tTAW / tCK;
memTimingSpec.RAS = tRAS / tCK;
memTimingSpec.RC = tRC / tCK;
memTimingSpec.RCD = tRCD / tCK;
memTimingSpec.REFI = tREFI / tCK;
memTimingSpec.RFC = tRFC / tCK;
memTimingSpec.RL = tRL / tCK;
memTimingSpec.RP = tRP / tCK;
memTimingSpec.RRD = tRRD / tCK;
memTimingSpec.RRD_L = tRRD / tCK;
memTimingSpec.RRD_S = tRRD / tCK;
memTimingSpec.RTP = defaultBurstLength;
memTimingSpec.TAW = tTAW / tCK;
memTimingSpec.WL = tWL / tCK;
memTimingSpec.WR = tWR / tCK;
memTimingSpec.WTR = tWTR / tCK;
memTimingSpec.WTR_L = tWTR / tCK;
memTimingSpec.WTR_S = tWTR / tCK;
memTimingSpec.XP = tXP / tCK;
memTimingSpec.XPDLL = tXP / tCK;
memTimingSpec.XS = tXSR / tCK;
memTimingSpec.XSDLL = tXSR / tCK;
DRAMPower::MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = iDD0;
memPowerSpec.idd02 = iDD02;
memPowerSpec.idd2p0 = iDD2P0;
memPowerSpec.idd2p02 = iDD2P02;
memPowerSpec.idd2p1 = iDD2P1;
memPowerSpec.idd2p12 = iDD2P12;
memPowerSpec.idd2n = iDD2N;
memPowerSpec.idd2n2 = iDD2N2;
memPowerSpec.idd3p0 = iDD3P0;
memPowerSpec.idd3p02 = iDD3P02;
memPowerSpec.idd3p1 = iDD3P1;
memPowerSpec.idd3p12 = iDD3P12;
memPowerSpec.idd3n = iDD3N;
memPowerSpec.idd3n2 = iDD3N2;
memPowerSpec.idd4r = iDD4R;
memPowerSpec.idd4r2 = iDD4R2;
memPowerSpec.idd4w = iDD4W;
memPowerSpec.idd4w2 = iDD4W2;
memPowerSpec.idd5 = iDD5;
memPowerSpec.idd52 = iDD52;
memPowerSpec.idd6 = iDD6;
memPowerSpec.idd62 = iDD62;
memPowerSpec.vdd = vDD;
memPowerSpec.vdd2 = vDD2;
DRAMPower::MemorySpecification powerSpec;
powerSpec.id = memoryId;
powerSpec.memoryType = DRAMPower::MemoryType::WIDEIO_SDR;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
return powerSpec;
}
#endif
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h
View File

@@ -107,6 +107,10 @@ public:
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
#endif
};
} // namespace DRAMSys

67
src/libdramsys/DRAMSys/simulation/DRAMSys.cpp
View File

@@ -43,26 +43,6 @@
#include "DRAMSys/common/DebugManager.h"
#include "DRAMSys/common/utils.h"
#include "DRAMSys/controller/Controller.h"
#include "DRAMSys/simulation/dram/DramDDR3.h"
#include "DRAMSys/simulation/dram/DramDDR4.h"
#include "DRAMSys/simulation/dram/DramGDDR5.h"
#include "DRAMSys/simulation/dram/DramGDDR5X.h"
#include "DRAMSys/simulation/dram/DramGDDR6.h"
#include "DRAMSys/simulation/dram/DramHBM2.h"
#include "DRAMSys/simulation/dram/DramLPDDR4.h"
#include "DRAMSys/simulation/dram/DramSTTMRAM.h"
#include "DRAMSys/simulation/dram/DramWideIO.h"
#include "DRAMSys/simulation/dram/DramWideIO2.h"
#ifdef DDR5_SIM
#include "DRAMSys/simulation/dram/DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "DRAMSys/simulation/dram/DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "DRAMSys/simulation/dram/DramHBM3.h"
#endif
#include <cstdlib>
#include <iostream>
@@ -183,57 +163,12 @@ void DRAMSys::instantiateModules(const ::DRAMSys::Config::AddressMapping& addres
arbiter = std::make_unique<ArbiterReorder>("arbiter", config, *addressDecoder);
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
controllers.emplace_back(std::make_unique<Controller>(
("controller" + std::to_string(i)).c_str(), config, *addressDecoder));
if (memoryType == MemSpec::MemoryType::DDR3)
drams.emplace_back(
std::make_unique<DramDDR3>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(
std::make_unique<DramDDR4>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(
std::make_unique<DramWideIO>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(
std::make_unique<DramLPDDR4>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(
std::make_unique<DramWideIO2>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::HBM2)
drams.emplace_back(
std::make_unique<DramHBM2>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::GDDR5)
drams.emplace_back(
std::make_unique<DramGDDR5>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
drams.emplace_back(
std::make_unique<DramGDDR5X>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::GDDR6)
drams.emplace_back(
std::make_unique<DramGDDR6>(("dram" + std::to_string(i)).c_str(), config));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(
std::make_unique<DramSTTMRAM>(("dram" + std::to_string(i)).c_str(), config));
#ifdef DDR5_SIM
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(
std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str(), config));
#endif
#ifdef LPDDR5_SIM
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(
std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), config));
#endif
#ifdef HBM3_SIM
else if (memoryType == MemSpec::MemoryType::HBM3)
drams.emplace_back(
std::make_unique<DramHBM3>(("dram" + std::to_string(i)).c_str(), config));
#endif
drams.emplace_back(std::make_unique<Dram>(("dram" + std::to_string(i)).c_str(), config));
if (config.checkTLM2Protocol)
controllersTlmCheckers.push_back(

68
src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp
View File

@@ -38,27 +38,7 @@
#include "DRAMSys/common/TlmRecorder.h"
#include "DRAMSys/controller/ControllerRecordable.h"
#include "DRAMSys/simulation/dram/DramDDR3.h"
#include "DRAMSys/simulation/dram/DramDDR4.h"
#include "DRAMSys/simulation/dram/DramGDDR5.h"
#include "DRAMSys/simulation/dram/DramGDDR5X.h"
#include "DRAMSys/simulation/dram/DramGDDR6.h"
#include "DRAMSys/simulation/dram/DramHBM2.h"
#include "DRAMSys/simulation/dram/DramLPDDR4.h"
#include "DRAMSys/simulation/dram/DramRecordable.h"
#include "DRAMSys/simulation/dram/DramSTTMRAM.h"
#include "DRAMSys/simulation/dram/DramWideIO.h"
#include "DRAMSys/simulation/dram/DramWideIO2.h"
#ifdef DDR5_SIM
#include "DRAMSys/simulation/dram/DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "DRAMSys/simulation/dram/DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "DRAMSys/simulation/dram/DramHBM3.h"
#endif
#include <memory>
@@ -142,57 +122,13 @@ void DRAMSysRecordable::instantiateModules(const std::string& traceName,
arbiter = std::make_unique<ArbiterReorder>("arbiter", config, *addressDecoder);
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
controllers.emplace_back(std::make_unique<ControllerRecordable>(
("controller" + std::to_string(i)).c_str(), config, *addressDecoder, tlmRecorders[i]));
if (memoryType == MemSpec::MemoryType::DDR3)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR3>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR4>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR4>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO2>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::HBM2)
drams.emplace_back(std::make_unique<DramRecordable<DramHBM2>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR5>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR5X>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR6)
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR6>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(std::make_unique<DramRecordable<DramSTTMRAM>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
#ifdef DDR5_SIM
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
#endif
#ifdef LPDDR5_SIM
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
#endif
#ifdef HBM3_SIM
else if (memoryType == MemSpec::MemoryType::HBM3)
drams.emplace_back(std::make_unique<DramRecordable<DramHBM3>>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
#endif
drams.emplace_back(std::make_unique<DramRecordable>(
("dram" + std::to_string(i)).c_str(), config, tlmRecorders[i]));
if (config.checkTLM2Protocol)
controllersTlmCheckers.emplace_back(

8
src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
View File

@@ -103,6 +103,14 @@ Dram::Dram(const sc_module_name& name, const Configuration& config) :
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
tSocket.register_b_transport(this, &Dram::b_transport);
tSocket.register_transport_dbg(this, &Dram::transport_dbg);
#ifdef DRAMPOWER
if (powerAnalysis)
{
const auto& memSpec = *config.memSpec;
DRAMPower = std::make_unique<libDRAMPower>(memSpec.toDramPowerMemSpec(), false);
}
#endif
}
Dram::~Dram()

18
src/libdramsys/DRAMSys/simulation/dram/Dram.h
View File

@@ -59,9 +59,6 @@ namespace DRAMSys
class Dram : public sc_core::sc_module, public Serialize, public Deserialize
{
protected:
Dram(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(Dram);
const MemSpec& memSpec;
// Data Storage:
@@ -82,6 +79,15 @@ protected:
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
public:
Dram(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(Dram);
Dram(const Dram&) = delete;
Dram(Dram&&) = delete;
Dram& operator=(const Dram&) = delete;
Dram& operator=(Dram&&) = delete;
~Dram() override;
static constexpr std::string_view BLOCKING_WARNING =
"Use the blocking mode of DRAMSys with caution! "
"The simulated timings do not reflect the real system!";
@@ -92,12 +98,6 @@ public:
void serialize(std::ostream& stream) const override;
void deserialize(std::istream& stream) override;
Dram(const Dram&) = delete;
Dram(Dram&&) = delete;
Dram& operator=(const Dram&) = delete;
Dram& operator=(Dram&&) = delete;
~Dram() override;
};
} // namespace DRAMSys

150
src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp
View File

@@ -1,150 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramDDR3.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
#ifdef DRAMPOWER
#include "LibDRAMPower.h"
using namespace DRAMPower;
#endif
using namespace sc_core;
namespace DRAMSys
{
DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
{
const auto* memSpecDDR3 = dynamic_cast<const MemSpecDDR3*>(config.memSpec.get());
if (memSpecDDR3 == nullptr)
SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen");
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpecDDR3->defaultBurstLength;
memArchSpec.dataRate = memSpecDDR3->dataRate;
memArchSpec.nbrOfRows = memSpecDDR3->rowsPerBank;
memArchSpec.nbrOfBanks = memSpecDDR3->banksPerChannel;
memArchSpec.nbrOfColumns = memSpecDDR3->columnsPerRow;
memArchSpec.nbrOfRanks = memSpecDDR3->ranksPerChannel;
memArchSpec.width = memSpecDDR3->bitWidth;
memArchSpec.nbrOfBankGroups = memSpecDDR3->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = false;
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = memSpecDDR3->tFAW / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RASB = memSpecDDR3->tRAS / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RCB = memSpecDDR3->tRC / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RPB = memSpecDDR3->tRP / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RRDB = memSpecDDR3->tRRD / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RRDB_L = memSpecDDR3->tRRD / memSpecDDR3->tCK;
// FIXME: memTimingSpec.RRDB_S = memSpecDDR3->tRRD / memSpecDDR3->tCK;
memTimingSpec.AL = memSpecDDR3->tAL / memSpecDDR3->tCK;
memTimingSpec.CCD = memSpecDDR3->tCCD / memSpecDDR3->tCK;
memTimingSpec.CCD_L = memSpecDDR3->tCCD / memSpecDDR3->tCK;
memTimingSpec.CCD_S = memSpecDDR3->tCCD / memSpecDDR3->tCK;
memTimingSpec.CKE = memSpecDDR3->tCKE / memSpecDDR3->tCK;
memTimingSpec.CKESR = memSpecDDR3->tCKESR / memSpecDDR3->tCK;
memTimingSpec.clkMhz = memSpecDDR3->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpecDDR3->fCKMHz;
memTimingSpec.DQSCK = memSpecDDR3->tDQSCK / memSpecDDR3->tCK;
memTimingSpec.FAW = memSpecDDR3->tFAW / memSpecDDR3->tCK;
memTimingSpec.RAS = memSpecDDR3->tRAS / memSpecDDR3->tCK;
memTimingSpec.RC = memSpecDDR3->tRC / memSpecDDR3->tCK;
memTimingSpec.RCD = memSpecDDR3->tRCD / memSpecDDR3->tCK;
memTimingSpec.REFI = memSpecDDR3->tREFI / memSpecDDR3->tCK;
memTimingSpec.RFC = memSpecDDR3->tRFC / memSpecDDR3->tCK;
memTimingSpec.RL = memSpecDDR3->tRL / memSpecDDR3->tCK;
memTimingSpec.RP = memSpecDDR3->tRP / memSpecDDR3->tCK;
memTimingSpec.RRD = memSpecDDR3->tRRD / memSpecDDR3->tCK;
memTimingSpec.RRD_L = memSpecDDR3->tRRD / memSpecDDR3->tCK;
memTimingSpec.RRD_S = memSpecDDR3->tRRD / memSpecDDR3->tCK;
memTimingSpec.RTP = memSpecDDR3->tRTP / memSpecDDR3->tCK;
memTimingSpec.TAW = memSpecDDR3->tFAW / memSpecDDR3->tCK;
memTimingSpec.WL = memSpecDDR3->tWL / memSpecDDR3->tCK;
memTimingSpec.WR = memSpecDDR3->tWR / memSpecDDR3->tCK;
memTimingSpec.WTR = memSpecDDR3->tWTR / memSpecDDR3->tCK;
memTimingSpec.WTR_L = memSpecDDR3->tWTR / memSpecDDR3->tCK;
memTimingSpec.WTR_S = memSpecDDR3->tWTR / memSpecDDR3->tCK;
memTimingSpec.XP = memSpecDDR3->tXP / memSpecDDR3->tCK;
memTimingSpec.XPDLL = memSpecDDR3->tXPDLL / memSpecDDR3->tCK;
memTimingSpec.XS = memSpecDDR3->tXS / memSpecDDR3->tCK;
memTimingSpec.XSDLL = memSpecDDR3->tXSDLL / memSpecDDR3->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpecDDR3->iDD0;
memPowerSpec.idd02 = 0;
memPowerSpec.idd2p0 = memSpecDDR3->iDD2P0;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = memSpecDDR3->iDD2P1;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = memSpecDDR3->iDD2N;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = memSpecDDR3->iDD3P0;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = memSpecDDR3->iDD3P1;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = memSpecDDR3->iDD3N;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = memSpecDDR3->iDD4R;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = memSpecDDR3->iDD4W;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = memSpecDDR3->iDD5;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = memSpecDDR3->iDD6;
memPowerSpec.idd62 = 0;
memPowerSpec.vdd = memSpecDDR3->vDD;
memPowerSpec.vdd2 = 0;
MemorySpecification powerSpec;
powerSpec.id = memSpecDDR3->memoryId;
powerSpec.memoryType = MemoryType::DDR3;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
}
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h
View File

@@ -1,55 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMDDR3_H
#define DRAMDDR3_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramDDR3 : public Dram
{
public:
DramDDR3(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramDDR3);
};
} // namespace DRAMSys
#endif // DRAMDDR3_H

150
src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp
View File

@@ -1,150 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramDDR4.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
#ifdef DRAMPOWER
#include "LibDRAMPower.h"
using namespace DRAMPower;
#endif
using namespace sc_core;
namespace DRAMSys
{
DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
{
const auto* memSpecDDR4 = dynamic_cast<const MemSpecDDR4*>(config.memSpec.get());
if (memSpecDDR4 == nullptr)
SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen");
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpecDDR4->defaultBurstLength;
memArchSpec.dataRate = memSpecDDR4->dataRate;
memArchSpec.nbrOfRows = memSpecDDR4->rowsPerBank;
memArchSpec.nbrOfBanks = memSpecDDR4->banksPerChannel;
memArchSpec.nbrOfColumns = memSpecDDR4->columnsPerRow;
memArchSpec.nbrOfRanks = memSpecDDR4->ranksPerChannel;
memArchSpec.width = memSpecDDR4->bitWidth;
memArchSpec.nbrOfBankGroups = memSpecDDR4->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = memSpecDDR4->tFAW / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RASB = memSpecDDR4->tRAS / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RCB = memSpecDDR4->tRC / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RPB = memSpecDDR4->tRP / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RRDB = memSpecDDR4->tRRD_S / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RRDB_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK;
// FIXME: memTimingSpec.RRDB_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK;
memTimingSpec.AL = memSpecDDR4->tAL / memSpecDDR4->tCK;
memTimingSpec.CCD = memSpecDDR4->tCCD_S / memSpecDDR4->tCK;
memTimingSpec.CCD_L = memSpecDDR4->tCCD_L / memSpecDDR4->tCK;
memTimingSpec.CCD_S = memSpecDDR4->tCCD_S / memSpecDDR4->tCK;
memTimingSpec.CKE = memSpecDDR4->tCKE / memSpecDDR4->tCK;
memTimingSpec.CKESR = memSpecDDR4->tCKESR / memSpecDDR4->tCK;
memTimingSpec.clkMhz = memSpecDDR4->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpecDDR4->fCKMHz;
memTimingSpec.DQSCK = memSpecDDR4->tDQSCK / memSpecDDR4->tCK;
memTimingSpec.FAW = memSpecDDR4->tFAW / memSpecDDR4->tCK;
memTimingSpec.RAS = memSpecDDR4->tRAS / memSpecDDR4->tCK;
memTimingSpec.RC = memSpecDDR4->tRC / memSpecDDR4->tCK;
memTimingSpec.RCD = memSpecDDR4->tRCD / memSpecDDR4->tCK;
memTimingSpec.REFI = memSpecDDR4->tREFI / memSpecDDR4->tCK;
memTimingSpec.RFC = memSpecDDR4->tRFC / memSpecDDR4->tCK;
memTimingSpec.RL = memSpecDDR4->tRL / memSpecDDR4->tCK;
memTimingSpec.RP = memSpecDDR4->tRP / memSpecDDR4->tCK;
memTimingSpec.RRD = memSpecDDR4->tRRD_S / memSpecDDR4->tCK;
memTimingSpec.RRD_L = memSpecDDR4->tRRD_L / memSpecDDR4->tCK;
memTimingSpec.RRD_S = memSpecDDR4->tRRD_S / memSpecDDR4->tCK;
memTimingSpec.RTP = memSpecDDR4->tRTP / memSpecDDR4->tCK;
memTimingSpec.TAW = memSpecDDR4->tFAW / memSpecDDR4->tCK;
memTimingSpec.WL = memSpecDDR4->tWL / memSpecDDR4->tCK;
memTimingSpec.WR = memSpecDDR4->tWR / memSpecDDR4->tCK;
memTimingSpec.WTR = memSpecDDR4->tWTR_S / memSpecDDR4->tCK;
memTimingSpec.WTR_L = memSpecDDR4->tWTR_L / memSpecDDR4->tCK;
memTimingSpec.WTR_S = memSpecDDR4->tWTR_S / memSpecDDR4->tCK;
memTimingSpec.XP = memSpecDDR4->tXP / memSpecDDR4->tCK;
memTimingSpec.XPDLL = memSpecDDR4->tXPDLL / memSpecDDR4->tCK;
memTimingSpec.XS = memSpecDDR4->tXS / memSpecDDR4->tCK;
memTimingSpec.XSDLL = memSpecDDR4->tXSDLL / memSpecDDR4->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpecDDR4->iDD0;
memPowerSpec.idd02 = memSpecDDR4->iDD02;
memPowerSpec.idd2p0 = memSpecDDR4->iDD2P0;
memPowerSpec.idd2p02 = 0;
memPowerSpec.idd2p1 = memSpecDDR4->iDD2P1;
memPowerSpec.idd2p12 = 0;
memPowerSpec.idd2n = memSpecDDR4->iDD2N;
memPowerSpec.idd2n2 = 0;
memPowerSpec.idd3p0 = memSpecDDR4->iDD3P0;
memPowerSpec.idd3p02 = 0;
memPowerSpec.idd3p1 = memSpecDDR4->iDD3P1;
memPowerSpec.idd3p12 = 0;
memPowerSpec.idd3n = memSpecDDR4->iDD3N;
memPowerSpec.idd3n2 = 0;
memPowerSpec.idd4r = memSpecDDR4->iDD4R;
memPowerSpec.idd4r2 = 0;
memPowerSpec.idd4w = memSpecDDR4->iDD4W;
memPowerSpec.idd4w2 = 0;
memPowerSpec.idd5 = memSpecDDR4->iDD5;
memPowerSpec.idd52 = 0;
memPowerSpec.idd6 = memSpecDDR4->iDD6;
memPowerSpec.idd62 = memSpecDDR4->iDD62;
memPowerSpec.vdd = memSpecDDR4->vDD;
memPowerSpec.vdd2 = memSpecDDR4->vDD2;
MemorySpecification powerSpec;
powerSpec.id = memSpecDDR4->memoryId;
powerSpec.memoryType = MemoryType::DDR4;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
}
#endif
}
} // namespace DRAMSys

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src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMDDR4_H
#define DRAMDDR4_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramDDR4 : public Dram
{
public:
DramDDR4(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramDDR4);
};
} // namespace DRAMSys
#endif // DRAMDDR4_H

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src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DRAMSys/simulation/dram/DramGDDR5.h"
using namespace sc_core;
namespace DRAMSys
{
DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramGDDR5", "DRAMPower does not support GDDR5");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMGDDR5_H
#define DRAMGDDR5_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramGDDR5 : public Dram
{
public:
DramGDDR5(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramGDDR5);
};
} // namespace DRAMSys
#endif // DRAMGDDR5_H

51
src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramGDDR5X.h"
using namespace sc_core;
namespace DRAMSys
{
DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramGDDR5X", "DRAMPower does not support GDDR5X");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMGDDR5X_H
#define DRAMGDDR5X_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramGDDR5X : public Dram
{
public:
DramGDDR5X(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramGDDR5X);
};
} // namespace DRAMSys
#endif // DRAMGDDR5X_H

51
src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramGDDR6.h"
using namespace sc_core;
namespace DRAMSys
{
DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramGDDR6", "DRAMPower does not support GDDR6");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMGDDR6_H
#define DRAMGDDR6_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramGDDR6 : public Dram
{
public:
DramGDDR6(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramGDDR6);
};
} // namespace DRAMSys
#endif // DRAMGDDR6_H

51
src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramHBM2.h"
using namespace sc_core;
namespace DRAMSys
{
DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramHBM2", "DRAMPower does not support HBM2");
#endif
}
} // namespace DRAMSys

54
src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMHBM2_H
#define DRAMHBM2_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramHBM2 : public Dram
{
public:
DramHBM2(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramHBM2);
};
} // namespace DRAMSys
#endif // DRAMHBM2_H

51
src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp
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/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramLPDDR4.h"
using namespace sc_core;
namespace DRAMSys
{
DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramLPDDR4", "DRAMPower does not support LPDDR4");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMLPDDR4_H
#define DRAMLPDDR4_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramLPDDR4 : public Dram
{
public:
DramLPDDR4(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramLPDDR4);
};
} // namespace DRAMSys
#endif // DRAMLPDDR4_H

60
src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp
View File

@@ -38,26 +38,6 @@
#include "DRAMSys/common/DebugManager.h"
#include "DRAMSys/common/TlmRecorder.h"
#include "DRAMSys/common/utils.h"
#include "DRAMSys/simulation/dram/DramDDR3.h"
#include "DRAMSys/simulation/dram/DramDDR4.h"
#include "DRAMSys/simulation/dram/DramGDDR5.h"
#include "DRAMSys/simulation/dram/DramGDDR5X.h"
#include "DRAMSys/simulation/dram/DramGDDR6.h"
#include "DRAMSys/simulation/dram/DramHBM2.h"
#include "DRAMSys/simulation/dram/DramLPDDR4.h"
#include "DRAMSys/simulation/dram/DramSTTMRAM.h"
#include "DRAMSys/simulation/dram/DramWideIO.h"
#include "DRAMSys/simulation/dram/DramWideIO2.h"
#ifdef DDR5_SIM
#include "DRAMSys/simulation/dram/DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "DRAMSys/simulation/dram/DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "DRAMSys/simulation/dram/DramHBM3.h"
#endif
using namespace sc_core;
using namespace tlm;
@@ -65,11 +45,10 @@ using namespace tlm;
namespace DRAMSys
{
template <typename BaseDram>
DramRecordable<BaseDram>::DramRecordable(const sc_module_name& name,
const Configuration& config,
TlmRecorder& tlmRecorder) :
BaseDram(name, config),
DramRecordable::DramRecordable(const sc_module_name& name,
const Configuration& config,
TlmRecorder& tlmRecorder) :
Dram(name, config),
tlmRecorder(tlmRecorder),
powerWindowSize(config.memSpec->tCK * config.windowSize)
{
@@ -81,9 +60,9 @@ DramRecordable<BaseDram>::DramRecordable(const sc_module_name& name,
#endif
}
template <typename BaseDram> void DramRecordable<BaseDram>::reportPower()
void DramRecordable::reportPower()
{
BaseDram::reportPower();
Dram::reportPower();
#ifdef DRAMPOWER
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power *
@@ -91,20 +70,19 @@ template <typename BaseDram> void DramRecordable<BaseDram>::reportPower()
#endif
}
template <typename BaseDram>
tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload& trans,
tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload& trans,
tlm_phase& phase,
sc_time& delay)
{
tlmRecorder.recordPhase(trans, phase, delay);
return BaseDram::nb_transport_fw(trans, phase, delay);
return Dram::nb_transport_fw(trans, phase, delay);
}
#ifdef DRAMPOWER
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for
// visualization purposes.
template <typename BaseDram> void DramRecordable<BaseDram>::powerWindow()
void DramRecordable::powerWindow()
{
int64_t clkCycles = 0;
@@ -140,24 +118,4 @@ template <typename BaseDram> void DramRecordable<BaseDram>::powerWindow()
}
#endif
template class DramRecordable<DramDDR3>;
template class DramRecordable<DramDDR4>;
template class DramRecordable<DramLPDDR4>;
template class DramRecordable<DramWideIO>;
template class DramRecordable<DramWideIO2>;
template class DramRecordable<DramGDDR5>;
template class DramRecordable<DramGDDR5X>;
template class DramRecordable<DramGDDR6>;
template class DramRecordable<DramHBM2>;
template class DramRecordable<DramSTTMRAM>;
#ifdef DDR5_SIM
template class DramRecordable<DramDDR5>;
#endif
#ifdef LPDDR5_SIM
template class DramRecordable<DramLPDDR5>;
#endif
#ifdef HBM3_SIM
template class DramRecordable<DramHBM3>;
#endif
} // namespace DRAMSys

3
src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h
View File

@@ -38,6 +38,7 @@
#include "DRAMSys/common/TlmRecorder.h"
#include "DRAMSys/configuration/Configuration.h"
#include "Dram.h"
#ifdef DRAMPOWER
#include "LibDRAMPower.h"
@@ -49,7 +50,7 @@
namespace DRAMSys
{
template <typename BaseDram> class DramRecordable final : public BaseDram
class DramRecordable : public Dram
{
public:
DramRecordable(const sc_core::sc_module_name& name,

52
src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp
View File

@@ -1,52 +0,0 @@
/*
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramSTTMRAM.h"
using namespace sc_core;
namespace DRAMSys
{
DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config) :
Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("DramSTTMRAM", "DRAMPower does not support STT-MRAM");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h
View File

@@ -1,55 +0,0 @@
/*
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMSTTMRAM_H
#define DRAMSTTMRAM_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramSTTMRAM : public Dram
{
public:
DramSTTMRAM(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramSTTMRAM);
};
} // namespace DRAMSys
#endif // DRAMSTTMRAM_H

152
src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp
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@@ -1,152 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramWideIO.h"
#include "DRAMSys/configuration/memspec/MemSpecWideIO.h"
#ifdef DRAMPOWER
#include "LibDRAMPower.h"
using namespace DRAMPower;
#endif
#include <memory>
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) : Dram(name, config)
{
#ifdef DRAMPOWER
if (powerAnalysis)
{
const auto* memSpecWideIO = dynamic_cast<const MemSpecWideIO*>(config.memSpec.get());
if (memSpecWideIO == nullptr)
SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen");
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpecWideIO->defaultBurstLength;
memArchSpec.dataRate = memSpecWideIO->dataRate;
memArchSpec.nbrOfRows = memSpecWideIO->rowsPerBank;
memArchSpec.nbrOfBanks = memSpecWideIO->banksPerChannel;
memArchSpec.nbrOfColumns = memSpecWideIO->columnsPerRow;
memArchSpec.nbrOfRanks = memSpecWideIO->ranksPerChannel;
memArchSpec.width = memSpecWideIO->bitWidth;
memArchSpec.nbrOfBankGroups = memSpecWideIO->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = false;
MemTimingSpec memTimingSpec;
// FIXME: memTimingSpec.FAWB = memSpecWideIO->tTAW / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RASB = memSpecWideIO->tRAS / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RCB = memSpecWideIO->tRC / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RPB = memSpecWideIO->tRP / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RRDB = memSpecWideIO->tRRD / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RRDB_L = memSpecWideIO->tRRD / memSpecWideIO->tCK;
// FIXME: memTimingSpec.RRDB_S = memSpecWideIO->tRRD / memSpecWideIO->tCK;
memTimingSpec.AL = 0;
memTimingSpec.CCD = memSpecWideIO->defaultBurstLength;
memTimingSpec.CCD_L = memSpecWideIO->defaultBurstLength;
memTimingSpec.CCD_S = memSpecWideIO->defaultBurstLength;
memTimingSpec.CKE = memSpecWideIO->tCKE / memSpecWideIO->tCK;
memTimingSpec.CKESR = memSpecWideIO->tCKESR / memSpecWideIO->tCK;
memTimingSpec.clkMhz = memSpecWideIO->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpecWideIO->fCKMHz;
memTimingSpec.DQSCK = memSpecWideIO->tDQSCK / memSpecWideIO->tCK;
memTimingSpec.FAW = memSpecWideIO->tTAW / memSpecWideIO->tCK;
memTimingSpec.RAS = memSpecWideIO->tRAS / memSpecWideIO->tCK;
memTimingSpec.RC = memSpecWideIO->tRC / memSpecWideIO->tCK;
memTimingSpec.RCD = memSpecWideIO->tRCD / memSpecWideIO->tCK;
memTimingSpec.REFI = memSpecWideIO->tREFI / memSpecWideIO->tCK;
memTimingSpec.RFC = memSpecWideIO->tRFC / memSpecWideIO->tCK;
memTimingSpec.RL = memSpecWideIO->tRL / memSpecWideIO->tCK;
memTimingSpec.RP = memSpecWideIO->tRP / memSpecWideIO->tCK;
memTimingSpec.RRD = memSpecWideIO->tRRD / memSpecWideIO->tCK;
memTimingSpec.RRD_L = memSpecWideIO->tRRD / memSpecWideIO->tCK;
memTimingSpec.RRD_S = memSpecWideIO->tRRD / memSpecWideIO->tCK;
memTimingSpec.RTP = memSpecWideIO->defaultBurstLength;
memTimingSpec.TAW = memSpecWideIO->tTAW / memSpecWideIO->tCK;
memTimingSpec.WL = memSpecWideIO->tWL / memSpecWideIO->tCK;
memTimingSpec.WR = memSpecWideIO->tWR / memSpecWideIO->tCK;
memTimingSpec.WTR = memSpecWideIO->tWTR / memSpecWideIO->tCK;
memTimingSpec.WTR_L = memSpecWideIO->tWTR / memSpecWideIO->tCK;
memTimingSpec.WTR_S = memSpecWideIO->tWTR / memSpecWideIO->tCK;
memTimingSpec.XP = memSpecWideIO->tXP / memSpecWideIO->tCK;
memTimingSpec.XPDLL = memSpecWideIO->tXP / memSpecWideIO->tCK;
memTimingSpec.XS = memSpecWideIO->tXSR / memSpecWideIO->tCK;
memTimingSpec.XSDLL = memSpecWideIO->tXSR / memSpecWideIO->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpecWideIO->iDD0;
memPowerSpec.idd02 = memSpecWideIO->iDD02;
memPowerSpec.idd2p0 = memSpecWideIO->iDD2P0;
memPowerSpec.idd2p02 = memSpecWideIO->iDD2P02;
memPowerSpec.idd2p1 = memSpecWideIO->iDD2P1;
memPowerSpec.idd2p12 = memSpecWideIO->iDD2P12;
memPowerSpec.idd2n = memSpecWideIO->iDD2N;
memPowerSpec.idd2n2 = memSpecWideIO->iDD2N2;
memPowerSpec.idd3p0 = memSpecWideIO->iDD3P0;
memPowerSpec.idd3p02 = memSpecWideIO->iDD3P02;
memPowerSpec.idd3p1 = memSpecWideIO->iDD3P1;
memPowerSpec.idd3p12 = memSpecWideIO->iDD3P12;
memPowerSpec.idd3n = memSpecWideIO->iDD3N;
memPowerSpec.idd3n2 = memSpecWideIO->iDD3N2;
memPowerSpec.idd4r = memSpecWideIO->iDD4R;
memPowerSpec.idd4r2 = memSpecWideIO->iDD4R2;
memPowerSpec.idd4w = memSpecWideIO->iDD4W;
memPowerSpec.idd4w2 = memSpecWideIO->iDD4W2;
memPowerSpec.idd5 = memSpecWideIO->iDD5;
memPowerSpec.idd52 = memSpecWideIO->iDD52;
memPowerSpec.idd6 = memSpecWideIO->iDD6;
memPowerSpec.idd62 = memSpecWideIO->iDD62;
memPowerSpec.vdd = memSpecWideIO->vDD;
memPowerSpec.vdd2 = memSpecWideIO->vDD2;
MemorySpecification powerSpec;
powerSpec.id = memSpecWideIO->memoryId;
powerSpec.memoryType = MemoryType::WIDEIO_SDR;
powerSpec.memTimingSpec = memTimingSpec;
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
}
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMWIDEIO_H
#define DRAMWIDEIO_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramWideIO : public Dram
{
public:
DramWideIO(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramWideIO);
};
} // namespace DRAMSys
#endif // DRAMWIDEIO_H

52
src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp
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@@ -1,52 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramWideIO2.h"
using namespace sc_core;
namespace DRAMSys
{
DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config) :
Dram(name, config)
{
#ifdef DRAMPOWER
if (config.powerAnalysis)
SC_REPORT_FATAL("DramWideIO2", "DRAMPower does not support WideIO2");
#endif
}
} // namespace DRAMSys

55
src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h
View File

@@ -1,55 +0,0 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMWIDEIO2_H
#define DRAMWIDEIO2_H
#include "DRAMSys/simulation/dram/Dram.h"
#include <systemc>
namespace DRAMSys
{
class DramWideIO2 : public Dram
{
public:
DramWideIO2(const sc_core::sc_module_name& name, const Configuration& config);
SC_HAS_PROCESS(DramWideIO2);
};
} // namespace DRAMSys
#endif // DRAMWIDEIO2_H