derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'work/namespacing' into 'develop'

Browse Source 
Namespace the complete DRAMSys library

See merge request ems/astdm/modeling.dram/dram.sys.5!21
This commit is contained in:
Lukas Steiner
2023-05-23 12:31:44 +00:00
parent fdb51f71ec 69cd04c448
commit ea40721ac0
164 changed files with 813 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -43,6 +43,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR5,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -275,3 +278,5 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
return {};
}
}
} // namespace DRAMSys

5
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
View File

@@ -40,6 +40,9 @@
#include <systemc>
#include <DRAMSys/configuration/memspec/MemSpec.h>
namespace DRAMSys
{
class MemSpecDDR5 final : public MemSpec
{
public:
@@ -127,4 +130,6 @@ public:
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys
#endif // MEMSPECDDR5_H

5
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
View File

@@ -41,6 +41,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
CheckerDDR5::CheckerDDR5(const Configuration& config)
{
memSpec = dynamic_cast<const MemSpecDDR5 *>(config.memSpec.get());
@@ -981,3 +984,5 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
last4ActivatesPhysical[physicalRank.ID()].push(lastCommandOnBus);
}
}
} // namespace DRAMSys

5
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h
View File

@@ -44,6 +44,9 @@
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/common/utils.h>
namespace DRAMSys
{
class CheckerDDR5 final : public CheckerIF
{
public:
@@ -108,4 +111,6 @@ private:
sc_core::sc_time tWRAPDEN;
};
} // namespace DRAMSys
#endif // CHECKERDDR5_H

5
extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp
View File

@@ -37,6 +37,9 @@
using namespace sc_core;
namespace DRAMSys
{
DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config)
: Dram(name, config)
{
@@ -45,3 +48,5 @@ DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config)
SC_REPORT_FATAL("DramDDR5", "DRAMPower does not support DDR5");
#endif
}
} // namespace DRAMSys

5
extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h
View File

@@ -40,6 +40,9 @@
#include <systemc>
namespace DRAMSys
{
class DramDDR5 : public Dram
{
public:
@@ -47,4 +50,6 @@ public:
SC_HAS_PROCESS(DramDDR5);
};
} // namespace DRAMSys
#endif // DRAMDDR5_H

5
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -42,6 +42,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM3,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -193,3 +196,5 @@ unsigned MemSpecHBM3::getRAAMMT() const
{
return RAAMMT;
}
} // namespace DRAMSys

5
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
View File

@@ -40,6 +40,9 @@
#include <systemc>
#include <DRAMSys/configuration/memspec/MemSpec.h>
namespace DRAMSys
{
class MemSpecHBM3 final : public MemSpec
{
public:
@@ -99,4 +102,6 @@ public:
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys
#endif // MemSpecHBM3_H

5
extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp
View File

@@ -41,6 +41,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
CheckerHBM3::CheckerHBM3(const Configuration &config)
{
memSpec = dynamic_cast<const MemSpecHBM3 *>(config.memSpec.get());
@@ -806,3 +809,5 @@ bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const
sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK;
return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME;
}
} // namespace DRAMSys

6
extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h
View File

@@ -44,6 +44,10 @@
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/common/utils.h>
namespace DRAMSys
{
class CheckerHBM3 final : public CheckerIF
{
public:
@@ -78,4 +82,6 @@ private:
sc_core::sc_time tWRRDL;
};
} // namespace DRAMSys
#endif // CHECKERHBM3_H

5
extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp
View File

@@ -40,6 +40,9 @@
using namespace sc_core;
namespace DRAMSys
{
DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config)
: Dram(name, config)
{
@@ -48,3 +51,5 @@ DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config)
SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3");
#endif
}
} // namespace DRAMSys

5
extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h
View File

@@ -40,6 +40,9 @@
#include <systemc>
namespace DRAMSys
{
class DramHBM3 : public Dram
{
public:
@@ -47,4 +50,6 @@ public:
SC_HAS_PROCESS(DramHBM3);
};
} // namespace DRAMSys
#endif // DRAMHBM3_H

5
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -42,6 +42,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::LPDDR5,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -244,3 +247,5 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
return {};
}
}
} // namespace DRAMSys

6
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
View File

@@ -41,6 +41,10 @@
#include <nlohmann/json.hpp>
namespace DRAMSys
{
class MemSpecLPDDR5 final : public MemSpec
{
public:
@@ -120,4 +124,6 @@ private:
unsigned per2BankOffset;
};
} // namespace DRAMSys
#endif // MEMSPECLPDDR5_H

5
extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp
View File

@@ -41,6 +41,9 @@
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
CheckerLPDDR5::CheckerLPDDR5(const Configuration& config)
{
memSpec = dynamic_cast<const MemSpecLPDDR5 *>(config.memSpec.get());
@@ -755,3 +758,5 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload)
last4Activates[rank.ID()].push(lastCommandOnBus);
}
}
} // namespace DRAMSys

5
extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h
View File

@@ -44,6 +44,9 @@
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/common/utils.h>
namespace DRAMSys
{
class CheckerLPDDR5 final : public CheckerIF
{
public:
@@ -82,4 +85,6 @@ private:
sc_core::sc_time tWRAPDEN;
};
} // namespace DRAMSys
#endif // CHECKERLPDDR5_H

6
extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp
View File

@@ -38,9 +38,11 @@
#include <DRAMSys/configuration/Configuration.h>
#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
using namespace sc_core;
namespace DRAMSys
{
DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config)
: Dram(name, config)
{
@@ -49,3 +51,5 @@ DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config)
SC_REPORT_FATAL("DramLPDDR5", "DRAMPower does not support LPDDR5");
#endif
}
} // namespace DRAMSys

5
extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h
View File

@@ -40,6 +40,9 @@
#include <systemc>
namespace DRAMSys
{
class DramLPDDR5 : public Dram
{
public:
@@ -47,4 +50,6 @@ public:
SC_HAS_PROCESS(DramLPDDR5);
};
} // namespace DRAMSys
#endif // DRAMLPDDR5_H