From 69cd04c4481ab84d2d31767dbbf6cd21cb243f4d Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 16 May 2023 11:27:16 +0200 Subject: [PATCH] Namespace the complete DRAMSys library --- .../configuration/memspec/MemSpecDDR5.cpp | 5 +++++ .../configuration/memspec/MemSpecDDR5.h | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR5.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR5.h | 5 +++++ .../DDR5/DRAMSys/simulation/dram/DramDDR5.cpp | 5 +++++ .../DDR5/DRAMSys/simulation/dram/DramDDR5.h | 5 +++++ .../configuration/memspec/MemSpecHBM3.cpp | 5 +++++ .../configuration/memspec/MemSpecHBM3.h | 5 +++++ .../DRAMSys/controller/checker/CheckerHBM3.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerHBM3.h | 6 ++++++ .../HBM3/DRAMSys/simulation/dram/DramHBM3.cpp | 5 +++++ .../HBM3/DRAMSys/simulation/dram/DramHBM3.h | 5 +++++ .../configuration/memspec/MemSpecLPDDR5.cpp | 5 +++++ .../configuration/memspec/MemSpecLPDDR5.h | 6 ++++++ .../controller/checker/CheckerLPDDR5.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerLPDDR5.h | 5 +++++ .../DRAMSys/simulation/dram/DramLPDDR5.cpp | 6 +++++- .../DRAMSys/simulation/dram/DramLPDDR5.h | 5 +++++ src/libdramsys/DRAMSys/common/DebugManager.cpp | 12 ++++++++---- src/libdramsys/DRAMSys/common/DebugManager.h | 14 ++++++-------- src/libdramsys/DRAMSys/common/TlmRecorder.cpp | 5 +++++ src/libdramsys/DRAMSys/common/TlmRecorder.h | 5 +++++ .../DRAMSys/common/dramExtensions.cpp | 5 +++++ src/libdramsys/DRAMSys/common/dramExtensions.h | 5 +++++ src/libdramsys/DRAMSys/common/utils.cpp | 5 +++++ src/libdramsys/DRAMSys/common/utils.h | 6 +++++- .../DRAMSys/configuration/Configuration.cpp | 5 +++++ .../DRAMSys/configuration/Configuration.h | 6 +++++- .../DRAMSys/configuration/memspec/MemSpec.cpp | 5 +++++ .../DRAMSys/configuration/memspec/MemSpec.h | 5 ++++- .../configuration/memspec/MemSpecDDR3.cpp | 5 +++++ .../configuration/memspec/MemSpecDDR3.h | 5 +++++ .../configuration/memspec/MemSpecDDR4.cpp | 5 +++++ .../configuration/memspec/MemSpecDDR4.h | 5 +++++ .../configuration/memspec/MemSpecGDDR5.cpp | 5 +++++ .../configuration/memspec/MemSpecGDDR5.h | 5 +++++ .../configuration/memspec/MemSpecGDDR5X.cpp | 5 +++++ .../configuration/memspec/MemSpecGDDR5X.h | 5 +++++ .../configuration/memspec/MemSpecGDDR6.cpp | 5 +++++ .../configuration/memspec/MemSpecGDDR6.h | 4 ++++ .../configuration/memspec/MemSpecHBM2.cpp | 5 +++++ .../configuration/memspec/MemSpecHBM2.h | 5 +++++ .../configuration/memspec/MemSpecLPDDR4.cpp | 5 +++++ .../configuration/memspec/MemSpecLPDDR4.h | 6 ++++++ .../configuration/memspec/MemSpecSTTMRAM.cpp | 5 +++++ .../configuration/memspec/MemSpecSTTMRAM.h | 5 +++++ .../configuration/memspec/MemSpecWideIO.cpp | 5 +++++ .../configuration/memspec/MemSpecWideIO.h | 5 +++++ .../configuration/memspec/MemSpecWideIO2.cpp | 5 +++++ .../configuration/memspec/MemSpecWideIO2.h | 5 +++++ .../DRAMSys/controller/BankMachine.cpp | 5 +++++ .../DRAMSys/controller/BankMachine.h | 5 +++++ src/libdramsys/DRAMSys/controller/Command.cpp | 4 ++++ src/libdramsys/DRAMSys/controller/Command.h | 7 ++++++- .../DRAMSys/controller/Controller.cpp | 5 +++++ src/libdramsys/DRAMSys/controller/Controller.h | 5 +++++ .../DRAMSys/controller/ControllerIF.h | 4 ++++ .../controller/ControllerRecordable.cpp | 5 +++++ .../DRAMSys/controller/ControllerRecordable.h | 5 +++++ src/libdramsys/DRAMSys/controller/ManagerIF.h | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR3.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR3.h | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR4.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerDDR4.h | 5 +++++ .../controller/checker/CheckerGDDR5.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerGDDR5.h | 5 +++++ .../controller/checker/CheckerGDDR5X.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerGDDR5X.h | 5 +++++ .../controller/checker/CheckerGDDR6.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerGDDR6.h | 5 +++++ .../DRAMSys/controller/checker/CheckerHBM2.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerHBM2.h | 5 +++++ .../DRAMSys/controller/checker/CheckerIF.h | 5 +++++ .../controller/checker/CheckerLPDDR4.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerLPDDR4.h | 5 +++++ .../controller/checker/CheckerSTTMRAM.cpp | 5 +++++ .../controller/checker/CheckerSTTMRAM.h | 5 +++++ .../controller/checker/CheckerWideIO.cpp | 5 +++++ .../DRAMSys/controller/checker/CheckerWideIO.h | 5 +++++ .../controller/checker/CheckerWideIO2.cpp | 5 +++++ .../controller/checker/CheckerWideIO2.h | 5 +++++ .../DRAMSys/controller/cmdmux/CmdMuxIF.h | 5 +++++ .../DRAMSys/controller/cmdmux/CmdMuxOldest.cpp | 5 +++++ .../DRAMSys/controller/cmdmux/CmdMuxOldest.h | 5 +++++ .../DRAMSys/controller/cmdmux/CmdMuxStrict.cpp | 5 +++++ .../DRAMSys/controller/cmdmux/CmdMuxStrict.h | 5 +++++ .../powerdown/PowerDownManagerDummy.cpp | 5 +++++ .../powerdown/PowerDownManagerDummy.h | 5 +++++ .../controller/powerdown/PowerDownManagerIF.h | 5 +++++ .../powerdown/PowerDownManagerStaggered.cpp | 5 +++++ .../powerdown/PowerDownManagerStaggered.h | 5 +++++ .../refresh/RefreshManagerAllBank.cpp | 7 ++++++- .../controller/refresh/RefreshManagerAllBank.h | 5 +++++ .../controller/refresh/RefreshManagerDummy.cpp | 7 ++++++- .../controller/refresh/RefreshManagerDummy.h | 5 +++++ .../controller/refresh/RefreshManagerIF.h | 5 +++++ .../refresh/RefreshManagerPer2Bank.cpp | 7 ++++++- .../refresh/RefreshManagerPer2Bank.h | 5 +++++ .../refresh/RefreshManagerPerBank.cpp | 7 ++++++- .../controller/refresh/RefreshManagerPerBank.h | 5 +++++ .../refresh/RefreshManagerSameBank.cpp | 5 +++++ .../refresh/RefreshManagerSameBank.h | 5 +++++ .../controller/respqueue/RespQueueFifo.cpp | 5 +++++ .../controller/respqueue/RespQueueFifo.h | 5 +++++ .../DRAMSys/controller/respqueue/RespQueueIF.h | 5 +++++ .../controller/respqueue/RespQueueReorder.cpp | 5 +++++ .../controller/respqueue/RespQueueReorder.h | 5 +++++ .../scheduler/BufferCounterBankwise.cpp | 7 ++++++- .../scheduler/BufferCounterBankwise.h | 5 +++++ .../controller/scheduler/BufferCounterIF.h | 5 +++++ .../scheduler/BufferCounterReadWrite.cpp | 7 ++++++- .../scheduler/BufferCounterReadWrite.h | 5 +++++ .../scheduler/BufferCounterShared.cpp | 5 +++++ .../controller/scheduler/BufferCounterShared.h | 5 +++++ .../controller/scheduler/SchedulerFifo.cpp | 5 +++++ .../controller/scheduler/SchedulerFifo.h | 5 +++++ .../controller/scheduler/SchedulerFrFcfs.cpp | 5 +++++ .../controller/scheduler/SchedulerFrFcfs.h | 5 +++++ .../scheduler/SchedulerFrFcfsGrp.cpp | 5 +++++ .../controller/scheduler/SchedulerFrFcfsGrp.h | 5 +++++ .../scheduler/SchedulerGrpFrFcfs.cpp | 5 +++++ .../controller/scheduler/SchedulerGrpFrFcfs.h | 5 +++++ .../scheduler/SchedulerGrpFrFcfsWm.cpp | 7 ++++++- .../scheduler/SchedulerGrpFrFcfsWm.h | 5 +++++ .../DRAMSys/controller/scheduler/SchedulerIF.h | 5 +++++ .../DRAMSys/simulation/AddressDecoder.cpp | 4 ++++ .../DRAMSys/simulation/AddressDecoder.h | 5 +++++ src/libdramsys/DRAMSys/simulation/Arbiter.cpp | 5 +++++ src/libdramsys/DRAMSys/simulation/Arbiter.h | 5 +++++ src/libdramsys/DRAMSys/simulation/DRAMSys.cpp | 7 ++++--- src/libdramsys/DRAMSys/simulation/DRAMSys.h | 5 +++-- .../DRAMSys/simulation/DRAMSysRecordable.cpp | 5 +++-- .../DRAMSys/simulation/DRAMSysRecordable.h | 5 +++-- .../DRAMSys/simulation/ReorderBuffer.h | 6 ++++-- .../DRAMSys/simulation/dram/Dram.cpp | 6 ++++++ src/libdramsys/DRAMSys/simulation/dram/Dram.h | 7 ++++++- .../DRAMSys/simulation/dram/DramDDR3.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramDDR3.h | 5 +++++ .../DRAMSys/simulation/dram/DramDDR4.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramDDR4.h | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR5.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR5.h | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR5X.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR5X.h | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR6.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramGDDR6.h | 4 ++++ .../DRAMSys/simulation/dram/DramHBM2.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramHBM2.h | 4 ++++ .../DRAMSys/simulation/dram/DramLPDDR4.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramLPDDR4.h | 5 +++++ .../DRAMSys/simulation/dram/DramRecordable.cpp | 7 ++++++- .../DRAMSys/simulation/dram/DramRecordable.h | 5 +++++ .../DRAMSys/simulation/dram/DramSTTMRAM.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramSTTMRAM.h | 5 +++++ .../DRAMSys/simulation/dram/DramWideIO.cpp | 4 ++++ .../DRAMSys/simulation/dram/DramWideIO.h | 5 +++++ .../DRAMSys/simulation/dram/DramWideIO2.cpp | 5 +++++ .../DRAMSys/simulation/dram/DramWideIO2.h | 5 +++++ src/simulator/main.cpp | 2 +- src/simulator/simulator/EccModule.cpp | 18 +++++++++--------- src/simulator/simulator/EccModule.h | 8 ++++---- tests/tests_dramsys/AddressDecoderTests.cpp | 8 ++++---- tests/tests_dramsys/Testfile.h | 2 +- .../tests_dramsys/b_transport/b_transport.cpp | 4 ++-- 164 files changed, 813 insertions(+), 58 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index d09907f1..9bdf808e 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::DDR5, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -275,3 +278,5 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen return {}; } } + +} // namespace DRAMSys diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index b8be3db3..dab2329a 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class MemSpecDDR5 final : public MemSpec { public: @@ -127,4 +130,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECDDR5_H diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index ffa12fe4..88ae5cdd 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerDDR5::CheckerDDR5(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -981,3 +984,5 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload) last4ActivatesPhysical[physicalRank.ID()].push(lastCommandOnBus); } } + +} // namespace DRAMSys diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h index 8bc3311f..c6ef773e 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h @@ -44,6 +44,9 @@ #include #include +namespace DRAMSys +{ + class CheckerDDR5 final : public CheckerIF { public: @@ -108,4 +111,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERDDR5_H diff --git a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp index 95c35db3..d4e043d7 100644 --- a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramDDR5", "DRAMPower does not support DDR5"); #endif } + +} // namespace DRAMSys diff --git a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h index 1e06dba3..591940ad 100644 --- a/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramDDR5 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramDDR5); }; +} // namespace DRAMSys + #endif // DRAMDDR5_H diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp index 18c96690..f3cb344a 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp @@ -42,6 +42,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::HBM3, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -193,3 +196,5 @@ unsigned MemSpecHBM3::getRAAMMT() const { return RAAMMT; } + +} // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h index 592e6353..2736d3fe 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class MemSpecHBM3 final : public MemSpec { public: @@ -99,4 +102,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MemSpecHBM3_H diff --git a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp index 0b375e0b..0f772f45 100644 --- a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerHBM3::CheckerHBM3(const Configuration &config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -806,3 +809,5 @@ bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK; return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME; } + +} // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h index f7da11e2..55fb58ad 100644 --- a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h @@ -44,6 +44,10 @@ #include #include +namespace DRAMSys +{ + + class CheckerHBM3 final : public CheckerIF { public: @@ -78,4 +82,6 @@ private: sc_core::sc_time tWRRDL; }; +} // namespace DRAMSys + #endif // CHECKERHBM3_H diff --git a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp index 62802a4d..dea2c104 100644 --- a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp @@ -40,6 +40,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -48,3 +51,5 @@ DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3"); #endif } + +} // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h index a5d2d67e..a08f0b13 100644 --- a/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramHBM3 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramHBM3); }; +} // namespace DRAMSys + #endif // DRAMHBM3_H diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 7fb0469b..f8784565 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -42,6 +42,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::LPDDR5, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -244,3 +247,5 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g return {}; } } + +} // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h index e3b91fa3..6ad60f93 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h @@ -41,6 +41,10 @@ #include +namespace DRAMSys +{ + + class MemSpecLPDDR5 final : public MemSpec { public: @@ -120,4 +124,6 @@ private: unsigned per2BankOffset; }; +} // namespace DRAMSys + #endif // MEMSPECLPDDR5_H diff --git a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp index b491c2b9..0a82bf22 100644 --- a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerLPDDR5::CheckerLPDDR5(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -755,3 +758,5 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(lastCommandOnBus); } } + +} // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h index 8590f3d6..05aaf5b7 100644 --- a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h @@ -44,6 +44,9 @@ #include #include +namespace DRAMSys +{ + class CheckerLPDDR5 final : public CheckerIF { public: @@ -82,4 +85,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERLPDDR5_H diff --git a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp index 156d0946..cb22f6f7 100644 --- a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp @@ -38,9 +38,11 @@ #include #include - using namespace sc_core; +namespace DRAMSys +{ + DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -49,3 +51,5 @@ DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramLPDDR5", "DRAMPower does not support LPDDR5"); #endif } + +} // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h index 62ce647b..46fa0c4f 100644 --- a/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramLPDDR5 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramLPDDR5); }; +} // namespace DRAMSys + #endif // DRAMLPDDR5_H diff --git a/src/libdramsys/DRAMSys/common/DebugManager.cpp b/src/libdramsys/DRAMSys/common/DebugManager.cpp index 4259e8fb..ce31973f 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.cpp +++ b/src/libdramsys/DRAMSys/common/DebugManager.cpp @@ -40,17 +40,18 @@ #include -using namespace sc_core; +namespace DRAMSys +{ void DebugManager::printDebugMessage(const std::string &sender, const std::string &message) { if (debugEnabled) { if (writeToConsole) - std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; if (writeToFile && debugFile) - debugFile << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + debugFile << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; } } @@ -63,7 +64,7 @@ void DebugManager::setup(bool _debugEnabled, bool _writeToConsole, bool _writeTo void DebugManager::printMessage(const std::string &sender, const std::string &message) { - std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; + std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; } void DebugManager::openDebugFile(const std::string &filename) @@ -86,4 +87,7 @@ DebugManager::~DebugManager() debugFile.close(); } } + +} // namespace DRAMSys + #endif diff --git a/src/libdramsys/DRAMSys/common/DebugManager.h b/src/libdramsys/DRAMSys/common/DebugManager.h index c8d0b7da..e3fee518 100644 --- a/src/libdramsys/DRAMSys/common/DebugManager.h +++ b/src/libdramsys/DRAMSys/common/DebugManager.h @@ -37,14 +37,6 @@ #ifndef DEBUGMANAGER_H #define DEBUGMANAGER_H -#if __has_cpp_attribute(maybe_unused) - #define NDEBUG_UNUSED(var_decl) [[maybe_unused]] var_decl -#elif (__GNUC__ || __clang__) - #define NDEBUG_UNUSED(var_decl) var_decl __attribute__((unused)) -#else - #define NDEBUG_UNUSED(var_decl) var_decl -#endif - #ifdef NDEBUG #define PRINTDEBUGMESSAGE(sender, message) {} #else @@ -53,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class DebugManager { public: @@ -84,6 +79,9 @@ private: std::ofstream debugFile; }; + +} // namespace DRAMSys + #endif #endif // DEBUGMANAGER_H diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp index e1e6d5b4..c679b85e 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.cpp +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.cpp @@ -49,6 +49,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) : name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME) @@ -524,3 +527,5 @@ void TlmRecorder::closeConnection() sqlite3_close(db); db = nullptr; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/TlmRecorder.h b/src/libdramsys/DRAMSys/common/TlmRecorder.h index 1b01a163..4402832b 100644 --- a/src/libdramsys/DRAMSys/common/TlmRecorder.h +++ b/src/libdramsys/DRAMSys/common/TlmRecorder.h @@ -56,6 +56,9 @@ class sqlite3; class sqlite3_stmt; +namespace DRAMSys +{ + class TlmRecorder { public: @@ -275,4 +278,6 @@ private: "CREATE INDEX \"messageTimes\" ON \"DebugMessages\" (\"Time\" ASC); \n"; }; +} // namespace DRAMSys + #endif // TLMRECORDER_H diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.cpp b/src/libdramsys/DRAMSys/common/dramExtensions.cpp index dead3e18..1111b745 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.cpp +++ b/src/libdramsys/DRAMSys/common/dramExtensions.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration) : thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration) @@ -458,3 +461,5 @@ bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans { return trans.get_extension()->notifyChildTransCompletion(); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index b920747b..9fd4c7ae 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class Thread { public: @@ -302,4 +305,6 @@ public: } }; +} // namespace DRAMSys + #endif // DRAMEXTENSIONS_H diff --git a/src/libdramsys/DRAMSys/common/utils.cpp b/src/libdramsys/DRAMSys/common/utils.cpp index 70df58d6..e7c793cf 100644 --- a/src/libdramsys/DRAMSys/common/utils.cpp +++ b/src/libdramsys/DRAMSys/common/utils.cpp @@ -44,6 +44,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + bool TimeInterval::timeIsInInterval(const sc_time &time) const { return (start < time && time < end); @@ -82,3 +85,5 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra ControllerExtension::setExtension(payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0); ArbiterExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), 0, SC_ZERO_TIME); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index f6c6a2c0..b8e7a0f5 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + class TimeInterval { public: @@ -66,5 +69,6 @@ std::string getPhaseName(const tlm::tlm_phase &phase); void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0)); -#endif // UTILS_H +} // namespace DRAMSys +#endif // UTILS_H diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.cpp b/src/libdramsys/DRAMSys/configuration/Configuration.cpp index 1661e8ec..1aeff517 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.cpp +++ b/src/libdramsys/DRAMSys/configuration/Configuration.cpp @@ -64,6 +64,9 @@ using namespace sc_core; +namespace DRAMSys +{ + enum sc_time_unit string2TimeUnit(const std::string &s) { if (s == "s") @@ -355,3 +358,5 @@ void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec &memSpecConfig) else SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/Configuration.h b/src/libdramsys/DRAMSys/configuration/Configuration.h index f9c7fff0..64a91407 100644 --- a/src/libdramsys/DRAMSys/configuration/Configuration.h +++ b/src/libdramsys/DRAMSys/configuration/Configuration.h @@ -49,6 +49,9 @@ #include #include +namespace DRAMSys +{ + class Configuration { public: @@ -104,5 +107,6 @@ public: void loadMemSpec(const DRAMSys::Config::MemSpec& memSpec); }; -#endif // CONFIGURATION_H +} // namespace DRAMSys +#endif // CONFIGURATION_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index 665763f6..66f53dd1 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -39,6 +39,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec, MemoryType memoryType, unsigned numberOfChannels, unsigned pseudoChannelsPerChannel, @@ -144,3 +147,5 @@ bool MemSpec::hasRasAndCasBus() const { return false; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index 21a105f4..f44d57d4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -48,6 +48,9 @@ #include #include +namespace DRAMSys +{ + class MemSpec { public: @@ -118,6 +121,6 @@ protected: uint64_t memorySizeBytes; }; +} // namespace DRAMSys #endif // MEMSPEC_H - diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index 719b3ba8..0d218d84 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::DDR3, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -160,3 +163,5 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_gen return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index a5c03d58..531354ce 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -42,6 +42,9 @@ #include +namespace DRAMSys +{ + class MemSpecDDR3 final : public MemSpec { public: @@ -96,4 +99,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECDDR3_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 89be15b6..e4c9e158 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::DDR4, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -179,3 +182,5 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tl return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 51b9d320..21b4b66d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecDDR4 final : public MemSpec { public: @@ -103,4 +106,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECDDR4_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index 10f59aac..4bfda168 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecGDDR5::MemSpecGDDR5(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::GDDR5, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -166,3 +169,5 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_ge return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index 72634e58..1436a2a0 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecGDDR5 final : public MemSpec { public: @@ -94,4 +97,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECGDDR5_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index d1e86148..f0fbc60e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::GDDR5X, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -166,3 +169,5 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_g return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 75faec54..f25f5314 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecGDDR5X final : public MemSpec { public: @@ -94,4 +97,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECGDDR5X_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index 127f331e..cdfa213e 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::GDDR6, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -179,3 +182,5 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_ge return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index 82711fbc..b9cee337 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -40,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" #include +namespace DRAMSys +{ struct MemSpecGDDR6 final : public MemSpec { @@ -101,4 +103,6 @@ private: unsigned per2BankOffset; }; +} // namespace DRAMSys + #endif // MEMSPECGDDR6_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index d3aa9e1f..9a8a4ff4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::HBM2, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -167,3 +170,5 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index b9d4e8a8..4b044b8f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecHBM2 final : public MemSpec { public: @@ -91,4 +94,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECHBM2_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index 3f72958e..c77866b9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::LPDDR4, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -169,3 +172,5 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_g return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 343677c5..ac146fad 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -41,6 +41,10 @@ #include +namespace DRAMSys +{ + + class MemSpecLPDDR4 final : public MemSpec { public: @@ -89,4 +93,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECLPDDR4_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index a46bbdbe..e13e5a2c 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::STTMRAM, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -135,3 +138,5 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm: return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index b31e2b2d..5fbb93ce 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecSTTMRAM final : public MemSpec { public: @@ -79,4 +82,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECSTTMRAM_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index 9092122f..f10c2378 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::WideIO, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -166,3 +169,5 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_g return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index e34a8892..abb399b9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecWideIO final : public MemSpec { public: @@ -101,4 +104,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECWIDEIO_H diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index 81462f78..91430ac4 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -43,6 +43,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + MemSpecWideIO2::MemSpecWideIO2(const DRAMSys::Config::MemSpec &memSpec) : MemSpec(memSpec, MemoryType::WideIO2, memSpec.memarchitecturespec.entries.at("nbrOfChannels"), @@ -154,3 +157,5 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_ return {}; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 8138e9ec..a19f6092 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class MemSpecWideIO2 final : public MemSpec { public: @@ -83,4 +86,6 @@ public: TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; +} // namespace DRAMSys + #endif // MEMSPECWIDEIO2_H diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.cpp b/src/libdramsys/DRAMSys/controller/BankMachine.cpp index bfa8e8ba..23f37813 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp +++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank) : scheduler(scheduler), memSpec(*config.memSpec), bank(bank), bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)), @@ -361,3 +364,5 @@ void BankMachineClosedAdaptive::evaluate() } } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/BankMachine.h b/src/libdramsys/DRAMSys/controller/BankMachine.h index 2b3fa701..ff5f6dd1 100644 --- a/src/libdramsys/DRAMSys/controller/BankMachine.h +++ b/src/libdramsys/DRAMSys/controller/BankMachine.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine : public ManagerIF { public: @@ -108,4 +111,6 @@ public: void evaluate() override; }; +} // namespace DRAMSys + #endif // BANKMACHINE_H diff --git a/src/libdramsys/DRAMSys/controller/Command.cpp b/src/libdramsys/DRAMSys/controller/Command.cpp index 1ad12525..285c6fe4 100644 --- a/src/libdramsys/DRAMSys/controller/Command.cpp +++ b/src/libdramsys/DRAMSys/controller/Command.cpp @@ -46,6 +46,8 @@ using namespace tlm; using namespace DRAMPower; #endif +namespace DRAMSys +{ bool phaseHasDataStrobe(tlm::tlm_phase phase) { @@ -246,3 +248,5 @@ bool Command::isRasCommand() const assert(type >= Command::NOP && type <= Command::SREFEX); return (type >= Command::ACT); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 75e982f1..0df2cdca 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -47,6 +47,9 @@ #include #include +namespace DRAMSys +{ + // DO NOT CHANGE THE ORDER! // BEGIN_REQ // 1 @@ -147,7 +150,7 @@ public: struct CommandTuple { - using Type = std::tuple<::Command, tlm::tlm_generic_payload*, sc_core::sc_time>; + using Type = std::tuple; enum Accessor { Command = 0, @@ -158,4 +161,6 @@ struct CommandTuple using ReadyCommands = std::vector; +} // namespace DRAMSys + #endif // COMMAND_H diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index affa7540..9eab47ff 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -76,6 +76,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : ControllerIF(name, config), addressDecoder(addressDecoder), thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw), @@ -685,3 +688,5 @@ bool Controller::isFullCycle(const sc_core::sc_time& time) const sc_time alignedAtHalfCycle = std::floor((time * 2 / memSpec.tCK + 0.5)) / 2 * memSpec.tCK; return sc_time::from_value(alignedAtHalfCycle.value() % memSpec.tCK.value()) == SC_ZERO_TIME; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/Controller.h b/src/libdramsys/DRAMSys/controller/Controller.h index d5cf89f9..8b8d36e7 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.h +++ b/src/libdramsys/DRAMSys/controller/Controller.h @@ -50,6 +50,9 @@ #include #include +namespace DRAMSys +{ + class Controller : public ControllerIF { public: @@ -124,4 +127,6 @@ private: } memoryManager; }; +} // namespace DRAMSys + #endif // CONTROLLER_H diff --git a/src/libdramsys/DRAMSys/controller/ControllerIF.h b/src/libdramsys/DRAMSys/controller/ControllerIF.h index 920c581d..a1fae197 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerIF.h +++ b/src/libdramsys/DRAMSys/controller/ControllerIF.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + // Utility class to pass around DRAMSys, without having to propagate the template definitions // throughout all classes class ControllerIF : public sc_core::sc_module @@ -164,5 +167,6 @@ protected: uint64_t numberOfBeatsServed = 0; }; +} // namespace DRAMSys #endif // CONTROLLERIF_H diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp index 241913d2..1c9c6d43 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp @@ -39,6 +39,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder) : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder), @@ -117,3 +120,5 @@ void ControllerRecordable::controllerMethod() Controller::controllerMethod(); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h index 125c188d..d0c011bc 100644 --- a/src/libdramsys/DRAMSys/controller/ControllerRecordable.h +++ b/src/libdramsys/DRAMSys/controller/ControllerRecordable.h @@ -41,6 +41,9 @@ #include #include +namespace DRAMSys +{ + class ControllerRecordable final : public Controller { public: @@ -73,4 +76,6 @@ private: const bool enableWindowing; }; +} // namespace DRAMSys + #endif // CONTROLLERRECORDABLE_H diff --git a/src/libdramsys/DRAMSys/controller/ManagerIF.h b/src/libdramsys/DRAMSys/controller/ManagerIF.h index 3b26adb3..65b4c4db 100644 --- a/src/libdramsys/DRAMSys/controller/ManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/ManagerIF.h @@ -37,6 +37,9 @@ #include "DRAMSys/controller/Command.h" +namespace DRAMSys +{ + class ManagerIF { public: @@ -46,4 +49,6 @@ public: virtual ~ManagerIF() = default; }; +} // namespace DRAMSys + #endif // MANAGERIF_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp index 52c22803..1ff43334 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerDDR3::CheckerDDR3(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -446,3 +449,5 @@ void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(sc_time_stamp()); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h index 154d15c3..4b3b99fe 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerDDR3 final : public CheckerIF { public: @@ -72,4 +75,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERDDR3_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp index b3f0b226..efadbbfd 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerDDR4::CheckerDDR4(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -479,3 +482,5 @@ void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(sc_time_stamp()); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h index 8740bca3..0ea82832 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h @@ -44,6 +44,9 @@ #include #include +namespace DRAMSys +{ + class CheckerDDR4 final : public CheckerIF { public: @@ -78,4 +81,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERDDR4_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp index 9eabb6aa..13e80761 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerGDDR5::CheckerGDDR5(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -568,3 +571,5 @@ void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload) if (command == Command::REFPB) bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h index 1b3e0b39..6268ff34 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerGDDR5 final : public CheckerIF { public: @@ -76,4 +79,6 @@ private: sc_core::sc_time tWRPRE; }; +} // namespace DRAMSys + #endif // CHECKERGDDR5_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp index a0eed3bd..bb70fcdd 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -572,3 +575,5 @@ void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload) if (command == Command::REFPB) bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h index ca2e17aa..3687c2a7 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerGDDR5X final : public CheckerIF { public: @@ -76,4 +79,6 @@ private: sc_core::sc_time tWRPRE; }; +} // namespace DRAMSys + #endif // CHECKERGDDR5X_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp index 447f9867..1e7cec88 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerGDDR6::CheckerGDDR6(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -585,3 +588,5 @@ void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload) if (command == Command::REFPB) bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h index 7f8b1340..6f451d68 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerGDDR6 final : public CheckerIF { public: @@ -74,4 +77,6 @@ private: sc_core::sc_time tWRPRE; }; +} // namespace DRAMSys + #endif // CHECKERGDDR6_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp index e4ff9f63..d3a2997b 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerHBM2::CheckerHBM2(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -549,3 +552,5 @@ void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload) if (command == Command::REFPB) bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h index 442ed36e..7630cbcf 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerHBM2 final : public CheckerIF { public: @@ -77,4 +80,6 @@ private: sc_core::sc_time tWRRDR; }; +} // namespace DRAMSys + #endif // CHECKERHBM2_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index 773a3d0e..d2c0e2f1 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -39,6 +39,9 @@ #include +namespace DRAMSys +{ + class CheckerIF { public: @@ -48,4 +51,6 @@ public: virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0; }; +} // namespace DRAMSys + #endif // CHECKERIF_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index 34d211bc..de26fa7f 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerLPDDR4::CheckerLPDDR4(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -534,3 +537,5 @@ void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(lastCommandOnBus); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h index 31ee2862..94b6295b 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerLPDDR4 final : public CheckerIF { public: @@ -80,4 +83,6 @@ private: sc_core::sc_time tREFPDEN; }; +} // namespace DRAMSys + #endif // CHECKERLPDDR4_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp index e3b43462..9f1bf0db 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -402,3 +405,5 @@ void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(sc_time_stamp()); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h index e95ccad8..09d7cd78 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerSTTMRAM final : public CheckerIF { public: @@ -72,4 +75,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERSTTMRAM_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp index c6b77185..8781e58d 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerWideIO::CheckerWideIO(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -422,3 +425,5 @@ void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload) last2Activates[rank.ID()].push(sc_time_stamp()); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h index cf30dfbc..3423782f 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerWideIO final : public CheckerIF { public: @@ -72,4 +75,6 @@ private: sc_core::sc_time tWRAPDEN; }; +} // namespace DRAMSys + #endif // CHECKERWIDEIO_H diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp index fa0052cb..e90a5c3a 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CheckerWideIO2::CheckerWideIO2(const Configuration& config) { memSpec = dynamic_cast(config.memSpec.get()); @@ -500,3 +503,5 @@ void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload) last4Activates[rank.ID()].push(sc_time_stamp()); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h index 6a890316..0b2bf188 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class CheckerWideIO2 final : public CheckerIF { public: @@ -73,4 +76,6 @@ private: sc_core::sc_time tWRRD_R; }; +} // namespace DRAMSys + #endif // CHECKERWIDEIO2_H diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h index f286f0de..c5e99d4f 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h @@ -37,6 +37,9 @@ #include "DRAMSys/controller/Command.h" +namespace DRAMSys +{ + class CmdMuxIF { public: @@ -44,4 +47,6 @@ public: virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0; }; +} // namespace DRAMSys + #endif // CMDMUXIF_H diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp index f9edeca9..e2c654d6 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp @@ -38,6 +38,9 @@ using namespace sc_core; +namespace DRAMSys +{ + CmdMuxOldest::CmdMuxOldest(const Configuration& config) : memSpec(*config.memSpec) {} CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommands) @@ -179,3 +182,5 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC else return {Command::NOP, nullptr, scMaxTime}; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h index cf6349ea..0009817d 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h @@ -38,6 +38,9 @@ #include "DRAMSys/controller/cmdmux/CmdMuxIF.h" #include "DRAMSys/configuration/Configuration.h" +namespace DRAMSys +{ + class CmdMuxOldest : public CmdMuxIF { public: @@ -64,4 +67,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // CMDMUXOLDEST_H diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp index bcc30072..be976484 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp @@ -38,6 +38,9 @@ using namespace sc_core; +namespace DRAMSys +{ + CmdMuxStrict::CmdMuxStrict(const Configuration& config) : memSpec(*config.memSpec) {} CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommands) @@ -182,3 +185,5 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC else return {Command::NOP, nullptr, scMaxTime}; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h index 16e77e9b..75470348 100644 --- a/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h +++ b/src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h @@ -38,6 +38,9 @@ #include "DRAMSys/controller/cmdmux/CmdMuxIF.h" #include "DRAMSys/configuration/Configuration.h" +namespace DRAMSys +{ + class CmdMuxStrict : public CmdMuxIF { public: @@ -65,4 +68,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // CMDMUXSTRICT_H diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp index 6f63c761..a4b56801 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp @@ -37,7 +37,12 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CommandTuple::Type PowerDownManagerDummy::getNextCommand() { return {Command::NOP, nullptr, SC_ZERO_TIME}; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h index 6ab4fab6..6a6f8c78 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h @@ -37,6 +37,9 @@ #include "DRAMSys/controller/powerdown/PowerDownManagerIF.h" +namespace DRAMSys +{ + class PowerDownManagerDummy final : public PowerDownManagerIF { public: @@ -51,4 +54,6 @@ public: void evaluate() override {} }; +} // namespace DRAMSys + #endif // POWERDOWNMANAGERDUMMY_H diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h index a88606c6..d6659c12 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class PowerDownManagerIF : public ManagerIF { public: @@ -48,4 +51,6 @@ public: virtual void triggerInterruption() = 0; }; +} // namespace DRAMSys + #endif // POWERDOWNMANAGERIF_H diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp index cb139700..e58d3a62 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp @@ -39,6 +39,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector& bankMachinesOnRank, Rank rank, CheckerIF& checker) : bankMachinesOnRank(bankMachinesOnRank) @@ -157,3 +160,5 @@ void PowerDownManagerStaggered::update(Command command) break; } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h index b035a09d..ee876345 100644 --- a/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h +++ b/src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h @@ -41,6 +41,9 @@ #include +namespace DRAMSys +{ + class BankMachine; class PowerDownManagerStaggered final : public PowerDownManagerIF @@ -69,4 +72,6 @@ private: bool enterSelfRefresh = false; }; +} // namespace DRAMSys + #endif // POWERDOWNMANAGERSTAGGERED_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp index eb88a2ec..437fadf2 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp @@ -41,6 +41,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), @@ -223,4 +226,6 @@ void RefreshManagerAllBank::update(Command command) sc_time RefreshManagerAllBank::getTimeForNextTrigger() { return timeForNextTrigger; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h index 68ffaa9c..f368e573 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h @@ -44,6 +44,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine; class PowerDownManagerIF; @@ -78,4 +81,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // REFRESHMANAGERALLBANK_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.cpp index 54b0caed..95756545 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.cpp @@ -37,6 +37,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + CommandTuple::Type RefreshManagerDummy::getNextCommand() { return {Command::NOP, nullptr, SC_ZERO_TIME}; @@ -45,4 +48,6 @@ CommandTuple::Type RefreshManagerDummy::getNextCommand() sc_time RefreshManagerDummy::getTimeForNextTrigger() { return scMaxTime; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h index 65c408d0..ba2cf07d 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h @@ -39,6 +39,9 @@ #include +namespace DRAMSys +{ + class RefreshManagerDummy final : public RefreshManagerIF { public: @@ -50,4 +53,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // REFRESHMANAGERDUMMY_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h index 0970f8da..8b9e6545 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class RefreshManagerIF : public ManagerIF { public: @@ -77,4 +80,6 @@ protected: } }; +} // namespace DRAMSys + #endif // REFRESHMANAGERIF_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp index e7a2cd1a..9a9ae45c 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp @@ -40,6 +40,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) @@ -246,4 +249,6 @@ void RefreshManagerPer2Bank::update(Command command) sc_time RefreshManagerPer2Bank::getTimeForNextTrigger() { return timeForNextTrigger; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h index db517555..25cc3c63 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine; class PowerDownManagerIF; @@ -83,4 +86,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // REFRESHMANAGERPER2BANK_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp index ff04f4dc..40ccb19f 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp @@ -40,6 +40,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) : powerDownManager(powerDownManager), memSpec(*config.memSpec), @@ -205,4 +208,6 @@ void RefreshManagerPerBank::update(Command command) sc_time RefreshManagerPerBank::getTimeForNextTrigger() { return timeForNextTrigger; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h index e7f88bff..8ceeff32 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine; class PowerDownManagerIF; @@ -82,4 +85,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // REFRESHMANAGERPERBANK_H diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp index ef7264e8..ffb48e8f 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.cpp @@ -40,6 +40,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + RefreshManagerSameBank::RefreshManagerSameBank(const Configuration& config, std::vector& bankMachinesOnRank, PowerDownManagerIF& powerDownManager, Rank rank) @@ -320,3 +323,5 @@ sc_time RefreshManagerSameBank::getTimeForNextTrigger() { return timeForNextTrigger; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h index d368c582..180384d9 100644 --- a/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h +++ b/src/libdramsys/DRAMSys/controller/refresh/RefreshManagerSameBank.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine; class PowerDownManagerIF; @@ -82,4 +85,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // REFRESHMANAGERSAMEBANK_H diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp index 234a52e9..fc0ed8a3 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.cpp @@ -37,6 +37,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + void RespQueueFifo::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd) { buffer.emplace(payload, strobeEnd); @@ -66,3 +69,5 @@ sc_time RespQueueFifo::getTriggerTime() const } return scMaxTime; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h index 253f4b72..ae0979a5 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueFifo.h @@ -42,6 +42,9 @@ #include #include +namespace DRAMSys +{ + class RespQueueFifo final : public RespQueueIF { public: @@ -54,4 +57,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // RESPQUEUEFIFO_H diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h index f9119ae1..928bad43 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueIF.h @@ -38,6 +38,9 @@ #include #include +namespace DRAMSys +{ + class RespQueueIF { public: @@ -47,4 +50,6 @@ public: virtual ~RespQueueIF() = default; }; +} // namespace DRAMSys + #endif // RESPQUEUEIF_H diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp index 4a425a14..5fa4eb63 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.cpp @@ -39,6 +39,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + void RespQueueReorder::insertPayload(tlm_generic_payload* payload, sc_time strobeEnd) { buffer[ControllerExtension::getChannelPayloadID(*payload)] = {payload, strobeEnd}; @@ -74,3 +77,5 @@ sc_time RespQueueReorder::getTriggerTime() const } return scMaxTime; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h index ccb69dbc..1a8870fc 100644 --- a/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h +++ b/src/libdramsys/DRAMSys/controller/respqueue/RespQueueReorder.h @@ -41,6 +41,9 @@ #include #include +namespace DRAMSys +{ + class RespQueueReorder final : public RespQueueIF { public: @@ -54,4 +57,6 @@ private: const sc_core::sc_time scMaxTime = sc_core::sc_max_time(); }; +} // namespace DRAMSys + #endif // RESPQUEUEREORDER_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp index 423ccfb1..509e36b8 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.cpp @@ -38,6 +38,9 @@ using namespace tlm; +namespace DRAMSys +{ + BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks) : requestBufferSize(requestBufferSize) { @@ -81,4 +84,6 @@ unsigned BufferCounterBankwise::getNumReadRequests() const unsigned BufferCounterBankwise::getNumWriteRequests() const { return numWriteRequests; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h index 4b70a819..cd75c47a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterBankwise.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class BufferCounterBankwise final : public BufferCounterIF { public: @@ -59,4 +62,6 @@ private: unsigned numWriteRequests = 0; }; +} // namespace DRAMSys + #endif // BUFFERCOUNTERBANKWISE_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h index 237cb9ea..e1632f39 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterIF.h @@ -38,6 +38,9 @@ #include #include +namespace DRAMSys +{ + class BufferCounterIF { public: @@ -50,4 +53,6 @@ public: [[nodiscard]] virtual unsigned getNumWriteRequests() const = 0; }; +} // namespace DRAMSys + #endif // BUFFERCOUNTERIF_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp index b794560c..c4255949 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.cpp @@ -36,6 +36,9 @@ using namespace tlm; +namespace DRAMSys +{ + BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize) : requestBufferSize(requestBufferSize) { @@ -76,4 +79,6 @@ unsigned BufferCounterReadWrite::getNumReadRequests() const unsigned BufferCounterReadWrite::getNumWriteRequests() const { return numReadWriteRequests[1]; -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h index 9ea6a971..b5d66a2a 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterReadWrite.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class BufferCounterReadWrite final : public BufferCounterIF { public: @@ -56,4 +59,6 @@ private: std::vector numReadWriteRequests; }; +} // namespace DRAMSys + #endif // BUFFERCOUNTERREADWRITE_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp index ae37069a..f5b89749 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.cpp @@ -36,6 +36,9 @@ using namespace tlm; +namespace DRAMSys +{ + BufferCounterShared::BufferCounterShared(unsigned requestBufferSize) : requestBufferSize(requestBufferSize) { @@ -79,3 +82,5 @@ unsigned BufferCounterShared::getNumWriteRequests() const { return numWriteRequests; } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h index 3c2880e3..bb33d8cd 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/BufferCounterShared.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class BufferCounterShared final : public BufferCounterIF { public: @@ -58,4 +61,6 @@ private: unsigned numWriteRequests = 0; }; +} // namespace DRAMSys + #endif // BUFFERCOUNTERSHARED_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp index 455f0507..c767674c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.cpp @@ -40,6 +40,9 @@ using namespace tlm; +namespace DRAMSys +{ + SchedulerFifo::SchedulerFifo(const Configuration& config) { buffer = std::vector>(config.memSpec->banksPerChannel); @@ -101,3 +104,5 @@ const std::vector& SchedulerFifo::getBufferDepth() const { return bufferCounter->getBufferDepth(); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h index f6dc34f7..44585171 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFifo.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class SchedulerFifo final : public SchedulerIF { public: @@ -62,4 +65,6 @@ private: std::unique_ptr bufferCounter; }; +} // namespace DRAMSys + #endif // SCHEDULERFIFO_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp index 076d8708..af8fa53c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.cpp @@ -40,6 +40,9 @@ using namespace tlm; +namespace DRAMSys +{ + SchedulerFrFcfs::SchedulerFrFcfs(const Configuration& config) { buffer = std::vector>(config.memSpec->banksPerChannel); @@ -122,3 +125,5 @@ const std::vector& SchedulerFrFcfs::getBufferDepth() const { return bufferCounter->getBufferDepth(); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h index 2526e890..f94e1831 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfs.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class SchedulerFrFcfs final : public SchedulerIF { public: @@ -62,4 +65,6 @@ private: std::unique_ptr bufferCounter; }; +} // namespace DRAMSys + #endif // SCHEDULERFRFCFS_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp index bb6bc990..3a5e7379 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -40,6 +40,9 @@ using namespace tlm; +namespace DRAMSys +{ + SchedulerFrFcfsGrp::SchedulerFrFcfsGrp(const Configuration& config) { buffer = std::vector>(config.memSpec->banksPerChannel); @@ -150,3 +153,5 @@ const std::vector& SchedulerFrFcfsGrp::getBufferDepth() const { return bufferCounter->getBufferDepth(); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h index 5b130188..da651e33 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class SchedulerFrFcfsGrp final : public SchedulerIF { public: @@ -63,4 +66,6 @@ private: std::unique_ptr bufferCounter; }; +} // namespace DRAMSys + #endif // SCHEDULERFRFCFSGRP_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp index cbc8b694..f76b7d60 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.cpp @@ -40,6 +40,9 @@ using namespace tlm; +namespace DRAMSys +{ + SchedulerGrpFrFcfs::SchedulerGrpFrFcfs(const Configuration& config) { readBuffer = std::vector>(config.memSpec->banksPerChannel); @@ -213,3 +216,5 @@ const std::vector& SchedulerGrpFrFcfs::getBufferDepth() const { return bufferCounter->getBufferDepth(); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h index 9078915e..61d86507 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + class SchedulerGrpFrFcfs final : public SchedulerIF { public: @@ -64,4 +67,6 @@ private: std::unique_ptr bufferCounter; }; +} // namespace DRAMSys + #endif // SCHEDULERGRPFRFCFS_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp index 32be6603..57a2dc28 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.cpp @@ -40,6 +40,9 @@ using namespace tlm; +namespace DRAMSys +{ + SchedulerGrpFrFcfsWm::SchedulerGrpFrFcfsWm(const Configuration& config) : lowWatermark(config.lowWatermark), highWatermark(config.highWatermark) { @@ -189,4 +192,6 @@ void SchedulerGrpFrFcfsWm::evaluateWriteMode() if (bufferCounter->getNumWriteRequests() > highWatermark || bufferCounter->getNumReadRequests() == 0) writeMode = true; } -} \ No newline at end of file +} + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h index 9e3932f2..ac70a20c 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + class SchedulerGrpFrFcfsWm final : public SchedulerIF { public: @@ -69,4 +72,6 @@ private: bool writeMode = false; }; +} // namespace DRAMSys + #endif // SCHEDULERGRPFRFCFSWM_H diff --git a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h index 87a3c7b6..7e3a79c0 100644 --- a/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h +++ b/src/libdramsys/DRAMSys/controller/scheduler/SchedulerIF.h @@ -40,6 +40,9 @@ #include #include +namespace DRAMSys +{ + class BankMachine; class SchedulerIF @@ -55,4 +58,6 @@ public: [[nodiscard]] virtual const std::vector& getBufferDepth() const = 0; }; +} // namespace DRAMSys + #endif // SCHEDULERIF_H diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp index 6ca432fb..73e70bfb 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp @@ -44,6 +44,9 @@ #include #include +namespace DRAMSys +{ + AddressDecoder::AddressDecoder(const DRAMSys::Config::AddressMapping &addressMapping, const MemSpec &memSpec) { if (const auto &channelBits = addressMapping.CHANNEL_BIT) @@ -339,3 +342,4 @@ void AddressDecoder::print() const std::cout << std::endl; } +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h index 42a9f0d3..d30d2554 100644 --- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.h +++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.h @@ -45,6 +45,9 @@ #include #include +namespace DRAMSys +{ + struct DecodedAddress { DecodedAddress(unsigned channel, unsigned rank, @@ -91,4 +94,6 @@ private: std::vector vByteBits; }; +} // namespace DRAMSys + #endif // ADDRESSDECODER_H diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp index ac6a060a..9ed5a92f 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.cpp +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.cpp @@ -48,6 +48,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + Arbiter::Arbiter(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) : sc_module(name), addressDecoder(addressDecoder), payloadEventQueue(this, &Arbiter::peqCallback), @@ -530,3 +533,5 @@ void ArbiterReorder::peqCallback(tlm_generic_payload& cbTrans, const tlm_phase& else SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase"); } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/Arbiter.h b/src/libdramsys/DRAMSys/simulation/Arbiter.h index a8eaef59..09599736 100644 --- a/src/libdramsys/DRAMSys/simulation/Arbiter.h +++ b/src/libdramsys/DRAMSys/simulation/Arbiter.h @@ -53,6 +53,9 @@ #include #include +namespace DRAMSys +{ + DECLARE_EXTENDED_PHASE(REQ_ARBITRATION); DECLARE_EXTENDED_PHASE(RESP_ARBITRATION); @@ -163,4 +166,6 @@ private: std::vector nextThreadPayloadIDToReturn; }; +} // namespace DRAMSys + #endif // ARBITER_H diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index 25e23c70..aa91c0a7 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -70,7 +70,8 @@ #include #include -namespace DRAMSys { +namespace DRAMSys +{ DRAMSys::DRAMSys(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib) @@ -142,7 +143,7 @@ void DRAMSys::logo() #undef BOLDTXT } -void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string& traceName)) const +void DRAMSys::setupDebugManager([[maybe_unused]] const std::string& traceName) const { #ifndef NDEBUG auto& dbg = DebugManager::getInstance(); @@ -239,4 +240,4 @@ void DRAMSys::report(const std::string& message) std::cout << message << std::endl; } -} \ No newline at end of file +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 84343589..cb94cd00 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -58,7 +58,8 @@ #include #include -namespace DRAMSys { +namespace DRAMSys +{ class DRAMSys : public sc_core::sc_module { @@ -107,6 +108,6 @@ private: void setupDebugManager(const std::string& traceName) const; }; -} +} // namespace DRAMSys #endif // DRAMSYS_H diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp index 6e892378..0fa5d35b 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.cpp @@ -62,7 +62,8 @@ #include -namespace DRAMSys { +namespace DRAMSys +{ DRAMSysRecordable::DRAMSysRecordable(const sc_core::sc_module_name& name, const ::DRAMSys::Config::Configuration& configLib) : DRAMSys(name, configLib, false) @@ -199,4 +200,4 @@ void DRAMSysRecordable::instantiateModules(const std::string& traceName, } } -} \ No newline at end of file +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h index b22315f0..3cbaa862 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSysRecordable.h @@ -42,7 +42,8 @@ #include "DRAMSys/config/DRAMSysConfiguration.h" -namespace DRAMSys { +namespace DRAMSys +{ class DRAMSysRecordable : public DRAMSys { @@ -62,6 +63,6 @@ private: void instantiateModules(const std::string& traceName, const ::DRAMSys::Config::Configuration& configLib); }; -} +} // namespace DRAMSys #endif // DRAMSYSRECORDABLE_H diff --git a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h index a69bbaef..94b297a0 100644 --- a/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h +++ b/src/libdramsys/DRAMSys/simulation/ReorderBuffer.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + struct ReorderBuffer : public sc_core::sc_module { public: @@ -159,7 +162,6 @@ private: }; - - +} // namespace DRAMSys #endif // REORDERBUFFER_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp index dea6203f..27239676 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp @@ -63,6 +63,10 @@ using namespace tlm; using namespace DRAMPower; #endif +namespace DRAMSys +{ + + Dram::Dram(const sc_module_name& name, const Configuration& config) : sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode), powerAnalysis(config.powerAnalysis), useMalloc(config.useMalloc) @@ -226,3 +230,5 @@ void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay) SC_REPORT_FATAL("DRAM", "Blocking transport not supported with error model yet."); } } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.h b/src/libdramsys/DRAMSys/simulation/dram/Dram.h index e30872db..f4c3aed2 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.h @@ -51,6 +51,10 @@ class libDRAMPower; +namespace DRAMSys +{ + + class Dram : public sc_core::sc_module { protected: @@ -85,5 +89,6 @@ public: ~Dram() override; }; -#endif // DRAM_H +} // namespace DRAMSys +#endif // DRAM_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp index 9f88c94f..24dbf557 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.cpp @@ -44,6 +44,9 @@ using namespace DRAMPower; using namespace sc_core; +namespace DRAMSys +{ + DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -144,3 +147,5 @@ DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config) } #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h index ee9e6cf9..cbdafdab 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR3.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramDDR3 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramDDR3); }; +} // namespace DRAMSys + #endif // DRAMDDR3_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp index 3a9c6575..f0edf157 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.cpp @@ -44,6 +44,9 @@ using namespace DRAMPower; using namespace sc_core; +namespace DRAMSys +{ + DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -144,3 +147,5 @@ DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config) } #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h index d51d71e9..b1a93a30 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramDDR4.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramDDR4 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramDDR4); }; +} // namespace DRAMSys + #endif // DRAMDDR4_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp index 515aa9a7..2a4c5cd6 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramGDDR5::DramGDDR5(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramGDDR5", "DRAMPower does not support GDDR5"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h index 645dfbee..327fe9c1 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramGDDR5 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramGDDR5); }; +} // namespace DRAMSys + #endif // DRAMGDDR5_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp index c1a3b334..84caa818 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramGDDR5X::DramGDDR5X(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramGDDR5X", "DRAMPower does not support GDDR5X"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h index bed8cc01..1bbbb17c 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR5X.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramGDDR5X : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramGDDR5X); }; +} // namespace DRAMSys + #endif // DRAMGDDR5X_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp index 7a8d0a11..3d3f49d7 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramGDDR6::DramGDDR6(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramGDDR6", "DRAMPower does not support GDDR6"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h index f2c82249..7c3ce9e2 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramGDDR6.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramGDDR6 : public Dram { public: @@ -47,5 +50,6 @@ public: SC_HAS_PROCESS(DramGDDR6); }; +} // namespace DRAMSys #endif // DRAMGDDR6_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp index f5891399..7e6d852b 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramHBM2::DramHBM2(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramHBM2", "DRAMPower does not support HBM2"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h index 2789a245..38dfc96a 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramHBM2.h @@ -40,6 +40,8 @@ #include +namespace DRAMSys +{ class DramHBM2 : public Dram { public: @@ -47,4 +49,6 @@ public: SC_HAS_PROCESS(DramHBM2); }; +} // namespace DRAMSys + #endif // DRAMHBM2_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp index 0134fcf3..05d49843 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramLPDDR4::DramLPDDR4(const sc_module_name& name, const Configuration& config) SC_REPORT_FATAL("DramLPDDR4", "DRAMPower does not support LPDDR4"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h index 94d93498..843fba50 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramLPDDR4.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramLPDDR4 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramLPDDR4); }; +} // namespace DRAMSys + #endif // DRAMLPDDR4_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp index 27d25f41..a9b60c60 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.cpp @@ -62,6 +62,9 @@ using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ + template DramRecordable::DramRecordable(const sc_module_name& name, const Configuration& config, TlmRecorder& tlmRecorder) @@ -150,4 +153,6 @@ template class DramRecordable; #endif #ifdef HBM3_SIM template class DramRecordable; -#endif \ No newline at end of file +#endif + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h index 3a2302c5..0453987e 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramRecordable.h @@ -46,6 +46,9 @@ #include #include +namespace DRAMSys +{ + template class DramRecordable final : public BaseDram { @@ -78,4 +81,6 @@ private: #endif }; +} // namespace DRAMSys + #endif // DRAMRECORDABLE_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp index d31c8fe1..4f301508 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config SC_REPORT_FATAL("DramSTTMRAM", "DRAMPower does not support STT-MRAM"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h index 647db1a0..8b324d11 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramSTTMRAM.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramSTTMRAM : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramSTTMRAM); }; +} // namespace DRAMSys + #endif // DRAMSTTMRAM_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp index 73daea18..aca3439b 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.cpp @@ -46,6 +46,8 @@ using namespace DRAMPower; using namespace sc_core; using namespace tlm; +namespace DRAMSys +{ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) : Dram(name, config) @@ -147,3 +149,5 @@ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config) } #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h index 523d2e30..7ab5531d 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramWideIO : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramWideIO); }; +} // namespace DRAMSys + #endif // DRAMWIDEIO_H diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp index a2d85c70..da7bd645 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.cpp @@ -37,6 +37,9 @@ using namespace sc_core; +namespace DRAMSys +{ + DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config) : Dram(name, config) { @@ -45,3 +48,5 @@ DramWideIO2::DramWideIO2(const sc_module_name& name, const Configuration& config SC_REPORT_FATAL("DramWideIO2", "DRAMPower does not support WideIO2"); #endif } + +} // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h index 9ba5329a..ca89e553 100644 --- a/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h +++ b/src/libdramsys/DRAMSys/simulation/dram/DramWideIO2.h @@ -40,6 +40,9 @@ #include +namespace DRAMSys +{ + class DramWideIO2 : public Dram { public: @@ -47,4 +50,6 @@ public: SC_HAS_PROCESS(DramWideIO2); }; +} // namespace DRAMSys + #endif // DRAMWIDEIO2_H diff --git a/src/simulator/main.cpp b/src/simulator/main.cpp index 67b0de76..3a270a29 100644 --- a/src/simulator/main.cpp +++ b/src/simulator/main.cpp @@ -84,7 +84,7 @@ int sc_main(int argc, char **argv) dramSys = std::make_unique("DRAMSys", configuration); } - bool storageEnabled = dramSys->getConfig().storeMode == Configuration::StoreMode::Store; + bool storageEnabled = dramSys->getConfig().storeMode == DRAMSys::Configuration::StoreMode::Store; MemoryManager memoryManager(storageEnabled); std::vector> initiators; diff --git a/src/simulator/simulator/EccModule.cpp b/src/simulator/simulator/EccModule.cpp index 6b3caa4f..2839f5e4 100644 --- a/src/simulator/simulator/EccModule.cpp +++ b/src/simulator/simulator/EccModule.cpp @@ -43,7 +43,7 @@ using namespace sc_core; using namespace tlm; -EccModule::EccModule(sc_module_name name, AddressDecoder const &addressDecoder) : +EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder) : sc_core::sc_module(name), payloadEventQueue(this, &EccModule::peqCallback), addressDecoder(addressDecoder), @@ -88,7 +88,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = SC_ZERO_TIME; - DecodedAddress decodedAddress = addressDecoder.decodeAddress(cbPayload.get_address()); + DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(cbPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); // Update the original address to account for the offsets @@ -129,7 +129,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ else if (cbPhase == END_REQ) // from target { // Send payload to inititator in case it is not an ECC transaction - if (cbPayload.get_extension() == nullptr) + if (cbPayload.get_extension() == nullptr) { tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; @@ -158,7 +158,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ tlm_phase tPhase = BEGIN_REQ; sc_time tDelay = SC_ZERO_TIME; - DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); + DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(tPayload.get_address()); decodedAddress = calculateOffsetAddress(decodedAddress); auto currentBlock = alignToBlock(decodedAddress.column); #ifdef ECC_ENABLE @@ -195,7 +195,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ else if (cbPhase == BEGIN_RESP) // from memory controller { // Send payload to inititator in case it is not an ECC transaction - if (cbPayload.get_extension() == nullptr) + if (cbPayload.get_extension() == nullptr) { tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = SC_ZERO_TIME; @@ -241,7 +241,7 @@ void EccModule::peqCallback(tlm::tlm_generic_payload &cbPayload, const tlm::tlm_ } } -tlm::tlm_generic_payload *EccModule::generateEccPayload(DecodedAddress decodedAddress) +tlm::tlm_generic_payload *EccModule::generateEccPayload(DRAMSys::DecodedAddress decodedAddress) { unsigned int eccAtom = decodedAddress.column / 512; uint64_t eccColumn = 1792 + eccAtom * 32; @@ -258,7 +258,7 @@ tlm::tlm_generic_payload *EccModule::generateEccPayload(DecodedAddress decodedAd payload.set_data_length(32); payload.set_streaming_width(32); payload.set_command(tlm::TLM_READ_COMMAND); - payload.set_extension(new EccExtension); + payload.set_extension(new DRAMSys::EccExtension); return &payload; } @@ -268,13 +268,13 @@ unsigned int EccModule::alignToBlock(unsigned column) return column & ~(512 - 1); } -DecodedAddress EccModule::calculateOffsetAddress(DecodedAddress decodedAddress) +DRAMSys::DecodedAddress EccModule::calculateOffsetAddress(DRAMSys::DecodedAddress decodedAddress) { unsigned int newRow = std::floor((decodedAddress.row * 256 + decodedAddress.column) / 1792) + decodedAddress.row; unsigned int newColumn = (decodedAddress.row * 256 + decodedAddress.column) % 1792; - DecodedAddress offsetAddress(decodedAddress); + DRAMSys::DecodedAddress offsetAddress(decodedAddress); offsetAddress.row = newRow; offsetAddress.column = newColumn; return offsetAddress; diff --git a/src/simulator/simulator/EccModule.h b/src/simulator/simulator/EccModule.h index 15817db3..d7f97090 100644 --- a/src/simulator/simulator/EccModule.h +++ b/src/simulator/simulator/EccModule.h @@ -55,7 +55,7 @@ public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; - EccModule(sc_core::sc_module_name name, AddressDecoder const &addressDecoder); + EccModule(sc_core::sc_module_name name, DRAMSys::AddressDecoder const &addressDecoder); SC_HAS_PROCESS(EccModule); private: @@ -65,7 +65,7 @@ private: using EccIdentifier = std::pair; using EccQueue = std::deque; - static DecodedAddress calculateOffsetAddress(DecodedAddress decodedAddress); + static DRAMSys::DecodedAddress calculateOffsetAddress(DRAMSys::DecodedAddress decodedAddress); static sc_core::sc_time roundLatency(sc_core::sc_time latency); bool activeEccBlock(Bank bank, Row row, Block block) const; @@ -80,7 +80,7 @@ private: tlm::tlm_phase &phase, sc_core::sc_time &bwDelay); - tlm::tlm_generic_payload *generateEccPayload(DecodedAddress decodedAddress); + tlm::tlm_generic_payload *generateEccPayload(DRAMSys::DecodedAddress decodedAddress); static unsigned int alignToBlock(unsigned int column); @@ -92,7 +92,7 @@ private: const sc_core::sc_time tCK; MemoryManager memoryManager; - AddressDecoder const &addressDecoder; + DRAMSys::AddressDecoder const &addressDecoder; std::unordered_map activeEccBlocks; diff --git a/tests/tests_dramsys/AddressDecoderTests.cpp b/tests/tests_dramsys/AddressDecoderTests.cpp index b7390555..6f1952a0 100644 --- a/tests/tests_dramsys/AddressDecoderTests.cpp +++ b/tests/tests_dramsys/AddressDecoderTests.cpp @@ -60,8 +60,8 @@ protected: DRAMSys::Config::AddressMapping addressMappingConfig; DRAMSys::Config::MemSpec memSpecConfig; - MemSpecLPDDR5 memSpec; - AddressDecoder addressDecoder; + DRAMSys::MemSpecLPDDR5 memSpec; + DRAMSys::AddressDecoder addressDecoder; }; TEST_F(AddressDecoderFixture, Decoding) @@ -96,7 +96,7 @@ TEST_F(AddressDecoderFixture, Encoding) unsigned int column = 170; unsigned int byte = 0; - DecodedAddress decodedAddress(channel, rank, bankgroup, bank, row, column, byte); + DRAMSys::DecodedAddress decodedAddress(channel, rank, bankgroup, bank, row, column, byte); uint64_t address = addressDecoder.encodeAddress(decodedAddress); EXPECT_EQ(address, 0x3A59'1474); @@ -111,7 +111,7 @@ TEST_F(AddressDecoderFixture, DeEncoding) for (auto address: testAddresses) { - DecodedAddress decodedAddress = addressDecoder.decodeAddress(address); + DRAMSys::DecodedAddress decodedAddress = addressDecoder.decodeAddress(address); uint64_t encodedAddress = addressDecoder.encodeAddress(decodedAddress); EXPECT_EQ(encodedAddress, address); diff --git a/tests/tests_dramsys/Testfile.h b/tests/tests_dramsys/Testfile.h index e381048b..96eddacd 100644 --- a/tests/tests_dramsys/Testfile.h +++ b/tests/tests_dramsys/Testfile.h @@ -39,5 +39,5 @@ TEST(testsuite, test) { - EXPECT_EQ(Command(Command::Type::ACT).toString(), "ACT"); + EXPECT_EQ(DRAMSys::Command(DRAMSys::Command::Type::ACT).toString(), "ACT"); } diff --git a/tests/tests_dramsys/b_transport/b_transport.cpp b/tests/tests_dramsys/b_transport/b_transport.cpp index 9fde8579..362c69e4 100644 --- a/tests/tests_dramsys/b_transport/b_transport.cpp +++ b/tests/tests_dramsys/b_transport/b_transport.cpp @@ -156,13 +156,13 @@ TEST_F(BTransportNoStorage, Warning) // Try to find the warning string std::string output = buffer.str(); - auto warning_pos = output.find(Dram::BLOCKING_WARNING); + auto warning_pos = output.find(DRAMSys::Dram::BLOCKING_WARNING); // Warning should be printed once ... EXPECT_NE(warning_pos, std::string::npos); // ... but not twice - warning_pos = output.find(Dram::BLOCKING_WARNING, warning_pos + 1); + warning_pos = output.find(DRAMSys::Dram::BLOCKING_WARNING, warning_pos + 1); EXPECT_EQ(warning_pos, std::string::npos); // Restore stdout