Namespace the complete DRAMSys library

extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::DDR5,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -275,3 +278,5 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
         return {};
     }
 }
+
+} // namespace DRAMSys

extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h

@@ -40,6 +40,9 @@
 #include <systemc>
 #include <DRAMSys/configuration/memspec/MemSpec.h>
 
+namespace DRAMSys
+{
+
 class MemSpecDDR5 final : public MemSpec
 {
 public:
@@ -127,4 +130,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECDDR5_H

extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerDDR5::CheckerDDR5(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecDDR5 *>(config.memSpec.get());
@@ -981,3 +984,5 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
         last4ActivatesPhysical[physicalRank.ID()].push(lastCommandOnBus);
     }
 }
+
+} // namespace DRAMSys

extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.h

@@ -44,6 +44,9 @@
 #include <DRAMSys/configuration/Configuration.h>
 #include <DRAMSys/common/utils.h>
 
+namespace DRAMSys
+{
+
 class CheckerDDR5 final : public CheckerIF
 {
 public:
@@ -108,4 +111,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERDDR5_H

extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.cpp

@@ -37,6 +37,9 @@
 
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config)
     : Dram(name, config)
 {
@@ -45,3 +48,5 @@ DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config)
         SC_REPORT_FATAL("DramDDR5", "DRAMPower does not support DDR5");
 #endif
 }
+
+} // namespace DRAMSys

extensions/standards/DDR5/DRAMSys/simulation/dram/DramDDR5.h

@@ -40,6 +40,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class DramDDR5 : public Dram
 {
 public:
@@ -47,4 +50,6 @@ public:
     SC_HAS_PROCESS(DramDDR5);
 };
 
+} // namespace DRAMSys
+
 #endif // DRAMDDR5_H

extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp

@@ -42,6 +42,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::HBM3,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -193,3 +196,5 @@ unsigned MemSpecHBM3::getRAAMMT() const
 {
     return RAAMMT;
 }
+
+} // namespace DRAMSys

extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h

@@ -40,6 +40,9 @@
 #include <systemc>
 #include <DRAMSys/configuration/memspec/MemSpec.h>
 
+namespace DRAMSys
+{
+
 class MemSpecHBM3 final : public MemSpec
 {
 public:
@@ -99,4 +102,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MemSpecHBM3_H

extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerHBM3::CheckerHBM3(const Configuration &config)
 {
     memSpec = dynamic_cast<const MemSpecHBM3 *>(config.memSpec.get());
@@ -806,3 +809,5 @@ bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const
     sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK;
     return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME;
 }
+
+} // namespace DRAMSys

extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.h

@@ -44,6 +44,10 @@
 #include <DRAMSys/configuration/Configuration.h>
 #include <DRAMSys/common/utils.h>
 
+namespace DRAMSys
+{
+
+
 class CheckerHBM3 final : public CheckerIF
 {
 public:
@@ -78,4 +82,6 @@ private:
     sc_core::sc_time tWRRDL;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERHBM3_H

extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.cpp

@@ -40,6 +40,9 @@
 
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config)
     : Dram(name, config)
 {
@@ -48,3 +51,5 @@ DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config)
         SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3");
 #endif
 }
+
+} // namespace DRAMSys

extensions/standards/HBM3/DRAMSys/simulation/dram/DramHBM3.h

@@ -40,6 +40,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class DramHBM3 : public Dram
 {
 public:
@@ -47,4 +50,6 @@ public:
     SC_HAS_PROCESS(DramHBM3);
 };
 
+} // namespace DRAMSys
+
 #endif // DRAMHBM3_H

extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp

@@ -42,6 +42,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::LPDDR5,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -244,3 +247,5 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
         return {};
     }
 }
+
+} // namespace DRAMSys

extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h

@@ -41,6 +41,10 @@
 
 #include <nlohmann/json.hpp>
 
+namespace DRAMSys
+{
+
+
 class MemSpecLPDDR5 final : public MemSpec
 {
 public:
@@ -120,4 +124,6 @@ private:
     unsigned per2BankOffset;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECLPDDR5_H

extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerLPDDR5::CheckerLPDDR5(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecLPDDR5 *>(config.memSpec.get());
@@ -755,3 +758,5 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(lastCommandOnBus);
     }
 }
+
+} // namespace DRAMSys

extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.h

@@ -44,6 +44,9 @@
 #include <DRAMSys/configuration/Configuration.h>
 #include <DRAMSys/common/utils.h>
 
+namespace DRAMSys
+{
+
 class CheckerLPDDR5 final : public CheckerIF
 {
 public:
@@ -82,4 +85,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERLPDDR5_H

extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.cpp

@@ -38,9 +38,11 @@
 #include <DRAMSys/configuration/Configuration.h>
 #include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
 
-
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config)
     : Dram(name, config)
 {
@@ -49,3 +51,5 @@ DramLPDDR5::DramLPDDR5(const sc_module_name& name, const Configuration& config)
         SC_REPORT_FATAL("DramLPDDR5", "DRAMPower does not support LPDDR5");
 #endif
 }
+
+} // namespace DRAMSys

extensions/standards/LPDDR5/DRAMSys/simulation/dram/DramLPDDR5.h

@@ -40,6 +40,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class DramLPDDR5 : public Dram
 {
 public:
@@ -47,4 +50,6 @@ public:
     SC_HAS_PROCESS(DramLPDDR5);
 };
 
+} // namespace DRAMSys
+
 #endif // DRAMLPDDR5_H

src/libdramsys/DRAMSys/common/DebugManager.cpp

@@ -40,17 +40,18 @@
 
 #include <DRAMSys/configuration/Configuration.h>
 
-using namespace sc_core;
+namespace DRAMSys
+{
 
 void DebugManager::printDebugMessage(const std::string &sender, const std::string &message)
 {
     if (debugEnabled)
     {
         if (writeToConsole)
-            std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
+            std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
 
         if (writeToFile && debugFile)
-            debugFile << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
+            debugFile << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
     }
 }
 
@@ -63,7 +64,7 @@ void DebugManager::setup(bool _debugEnabled, bool _writeToConsole, bool _writeTo
 
 void DebugManager::printMessage(const std::string &sender, const std::string &message)
 {
-    std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
+    std::cout << " at " << sc_core::sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
 }
 
 void DebugManager::openDebugFile(const std::string &filename)
@@ -86,4 +87,7 @@ DebugManager::~DebugManager()
         debugFile.close();
     }
 }
+
+} // namespace DRAMSys
+
 #endif

src/libdramsys/DRAMSys/common/DebugManager.h

@@ -37,14 +37,6 @@
 #ifndef DEBUGMANAGER_H
 #define DEBUGMANAGER_H
 
-#if __has_cpp_attribute(maybe_unused)
-    #define NDEBUG_UNUSED(var_decl) [[maybe_unused]] var_decl
-#elif (__GNUC__ || __clang__)
-    #define NDEBUG_UNUSED(var_decl) var_decl __attribute__((unused))
-#else
-    #define	NDEBUG_UNUSED(var_decl) var_decl
-#endif
-
 #ifdef NDEBUG
 #define PRINTDEBUGMESSAGE(sender, message) {}
 #else
@@ -53,6 +45,9 @@
 #include <string>
 #include <fstream>
 
+namespace DRAMSys
+{
+
 class DebugManager
 {
 public:
@@ -84,6 +79,9 @@ private:
 
     std::ofstream debugFile;
 };
+
+} // namespace DRAMSys
+
 #endif
 
 #endif // DEBUGMANAGER_H

src/libdramsys/DRAMSys/common/TlmRecorder.cpp

@@ -49,6 +49,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 TlmRecorder::TlmRecorder(const std::string& name, const Configuration& config, const std::string& dbName) :
         name(name), config(config), memSpec(*config.memSpec), totalNumTransactions(0),
         simulationTimeCoveredByRecording(SC_ZERO_TIME)
@@ -524,3 +527,5 @@ void TlmRecorder::closeConnection()
     sqlite3_close(db);
     db = nullptr;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/common/TlmRecorder.h

@@ -56,6 +56,9 @@
 class sqlite3;
 class sqlite3_stmt;
 
+namespace DRAMSys
+{
+
 class TlmRecorder
 {
 public:
@@ -275,4 +278,6 @@ private:
         "CREATE INDEX \"messageTimes\" ON \"DebugMessages\" (\"Time\" ASC);                                        \n";
 };
 
+} // namespace DRAMSys
+
 #endif // TLMRECORDER_H

src/libdramsys/DRAMSys/common/dramExtensions.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 ArbiterExtension::ArbiterExtension(Thread thread, Channel channel, uint64_t threadPayloadID,
                                    const sc_core::sc_time& timeOfGeneration) :
         thread(thread), channel(channel), threadPayloadID(threadPayloadID), timeOfGeneration(timeOfGeneration)
@@ -458,3 +461,5 @@ bool ParentExtension::notifyChildTransCompletion(tlm::tlm_generic_payload& trans
 {
     return trans.get_extension<ParentExtension>()->notifyChildTransCompletion();
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/common/dramExtensions.h

@@ -42,6 +42,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class Thread
 {
 public:
@@ -302,4 +305,6 @@ public:
     }
 };
 
+} // namespace DRAMSys
+
 #endif // DRAMEXTENSIONS_H

src/libdramsys/DRAMSys/common/utils.cpp

@@ -44,6 +44,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 bool TimeInterval::timeIsInInterval(const sc_time &time) const
 {
     return (start < time && time < end);
@@ -82,3 +85,5 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra
     ControllerExtension::setExtension(payload, channelPayloadID, rank, bankGroup, bank, Row(0), Column(0), 0);
     ArbiterExtension::setExtension(payload, Thread(UINT_MAX), Channel(0), 0, SC_ZERO_TIME);
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/common/utils.h

@@ -46,6 +46,9 @@
 #include <tlm>
 #include <string>
 
+namespace DRAMSys
+{
+
 class TimeInterval
 {
 public:
@@ -66,5 +69,6 @@ std::string getPhaseName(const tlm::tlm_phase &phase);
 void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID,
                 Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0));
 
-#endif // UTILS_H
+} // namespace DRAMSys
 
+#endif // UTILS_H

src/libdramsys/DRAMSys/configuration/Configuration.cpp

@@ -64,6 +64,9 @@
 
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 enum sc_time_unit string2TimeUnit(const std::string &s)
 {
     if (s == "s")
@@ -355,3 +358,5 @@ void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec &memSpecConfig)
     else
         SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/Configuration.h

@@ -49,6 +49,9 @@
 #include <systemc>
 #include <string>
 
+namespace DRAMSys
+{
+
 class Configuration
 {
 public:
@@ -104,5 +107,6 @@ public:
     void loadMemSpec(const DRAMSys::Config::MemSpec& memSpec);
 };
 
-#endif // CONFIGURATION_H
+} // namespace DRAMSys
 
+#endif // CONFIGURATION_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp

@@ -39,6 +39,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec,
     MemoryType memoryType,
     unsigned numberOfChannels, unsigned pseudoChannelsPerChannel,
@@ -144,3 +147,5 @@ bool MemSpec::hasRasAndCasBus() const
 {
     return false;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h

@@ -48,6 +48,9 @@
 #include <vector>
 #include <string>
 
+namespace DRAMSys
+{
+
 class MemSpec
 {
 public:
@@ -118,6 +121,6 @@ protected:
     uint64_t memorySizeBytes;
 };
 
+} // namespace DRAMSys
 
 #endif // MEMSPEC_H
-

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecDDR3::MemSpecDDR3(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::DDR3,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -160,3 +163,5 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_gen
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h

@@ -42,6 +42,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecDDR3 final : public MemSpec
 {
 public:
@@ -96,4 +99,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECDDR3_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecDDR4::MemSpecDDR4(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::DDR4,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -179,3 +182,5 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tl
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecDDR4 final : public MemSpec
 {
 public:
@@ -103,4 +106,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECDDR4_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecGDDR5::MemSpecGDDR5(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::GDDR5,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -166,3 +169,5 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_ge
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecGDDR5 final : public MemSpec
 {
 public:
@@ -94,4 +97,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECGDDR5_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::GDDR5X,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -166,3 +169,5 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_g
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecGDDR5X final : public MemSpec
 {
 public:
@@ -94,4 +97,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECGDDR5X_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecGDDR6::MemSpecGDDR6(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::GDDR6,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -179,3 +182,5 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_ge
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h

@@ -40,6 +40,8 @@
 #include "DRAMSys/configuration/memspec/MemSpec.h"
 
 #include <systemc>
+namespace DRAMSys
+{
 
 struct MemSpecGDDR6 final : public MemSpec
 {
@@ -101,4 +103,6 @@ private:
     unsigned per2BankOffset;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECGDDR6_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::HBM2,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -167,3 +170,5 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecHBM2 final : public MemSpec
 {
 public:
@@ -91,4 +94,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECHBM2_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::LPDDR4,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -169,3 +172,5 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_g
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h

@@ -41,6 +41,10 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
+
 class MemSpecLPDDR4 final : public MemSpec
 {
 public:
@@ -89,4 +93,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECLPDDR4_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::STTMRAM,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -135,3 +138,5 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm:
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecSTTMRAM final : public MemSpec
 {
 public:
@@ -79,4 +82,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECSTTMRAM_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecWideIO::MemSpecWideIO(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::WideIO,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -166,3 +169,5 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_g
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecWideIO final : public MemSpec
 {
 public:
@@ -101,4 +104,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECWIDEIO_H

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp

@@ -43,6 +43,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 MemSpecWideIO2::MemSpecWideIO2(const DRAMSys::Config::MemSpec &memSpec)
     : MemSpec(memSpec, MemoryType::WideIO2,
       memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
@@ -154,3 +157,5 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_
         return {};
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class MemSpecWideIO2 final : public MemSpec
 {
 public:
@@ -83,4 +86,6 @@ public:
     TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
+} // namespace DRAMSys
+
 #endif // MEMSPECWIDEIO2_H

src/libdramsys/DRAMSys/controller/BankMachine.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank)
     : scheduler(scheduler), memSpec(*config.memSpec), bank(bank),
     bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)),
@@ -361,3 +364,5 @@ void BankMachineClosedAdaptive::evaluate()
         }
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/BankMachine.h

@@ -46,6 +46,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class BankMachine : public ManagerIF
 {
 public:
@@ -108,4 +111,6 @@ public:
     void evaluate() override;
 };
 
+} // namespace DRAMSys
+
 #endif // BANKMACHINE_H

src/libdramsys/DRAMSys/controller/Command.cpp

@@ -46,6 +46,8 @@ using namespace tlm;
 using namespace DRAMPower;
 #endif
 
+namespace DRAMSys
+{
 
 bool phaseHasDataStrobe(tlm::tlm_phase phase)
 {
@@ -246,3 +248,5 @@ bool Command::isRasCommand() const
     assert(type >= Command::NOP && type <= Command::SREFEX);
     return (type >= Command::ACT);
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/Command.h

@@ -47,6 +47,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 // DO NOT CHANGE THE ORDER!
 
 //                     BEGIN_REQ      // 1
@@ -147,7 +150,7 @@ public:
 
 struct CommandTuple
 {
-    using Type = std::tuple<::Command, tlm::tlm_generic_payload*, sc_core::sc_time>;
+    using Type = std::tuple<DRAMSys::Command, tlm::tlm_generic_payload*, sc_core::sc_time>;
     enum Accessor
     {
         Command = 0,
@@ -158,4 +161,6 @@ struct CommandTuple
 
 using ReadyCommands = std::vector<CommandTuple::Type>;
 
+} // namespace DRAMSys
+
 #endif // COMMAND_H

src/libdramsys/DRAMSys/controller/Controller.cpp

@@ -76,6 +76,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 Controller::Controller(const sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder) :
     ControllerIF(name, config), addressDecoder(addressDecoder),
     thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw),
@@ -685,3 +688,5 @@ bool Controller::isFullCycle(const sc_core::sc_time& time) const
     sc_time alignedAtHalfCycle = std::floor((time * 2 / memSpec.tCK + 0.5)) / 2 * memSpec.tCK;
     return sc_time::from_value(alignedAtHalfCycle.value() % memSpec.tCK.value()) == SC_ZERO_TIME;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/Controller.h

@@ -50,6 +50,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class Controller : public ControllerIF
 {
 public:
@@ -124,4 +127,6 @@ private:
     } memoryManager;
 };
 
+} // namespace DRAMSys
+
 #endif // CONTROLLER_H

src/libdramsys/DRAMSys/controller/ControllerIF.h

@@ -46,6 +46,9 @@
 #include <tlm_utils/simple_initiator_socket.h>
 #include <tlm_utils/simple_target_socket.h>
 
+namespace DRAMSys
+{
+
 // Utility class to pass around DRAMSys, without having to propagate the template definitions
 // throughout all classes
 class ControllerIF : public sc_core::sc_module
@@ -164,5 +167,6 @@ protected:
     uint64_t numberOfBeatsServed = 0;
 };
 
+} // namespace DRAMSys
 
 #endif // CONTROLLERIF_H

src/libdramsys/DRAMSys/controller/ControllerRecordable.cpp

@@ -39,6 +39,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 ControllerRecordable::ControllerRecordable(const sc_module_name& name, const Configuration& config,
                                            const AddressDecoder& addressDecoder, TlmRecorder& tlmRecorder)
     : Controller(name, config, addressDecoder), tlmRecorder(tlmRecorder),
@@ -117,3 +120,5 @@ void ControllerRecordable::controllerMethod()
         Controller::controllerMethod();
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/ControllerRecordable.h

@@ -41,6 +41,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class ControllerRecordable final : public Controller
 {
 public:
@@ -73,4 +76,6 @@ private:
     const bool enableWindowing;
 };
 
+} // namespace DRAMSys
+
 #endif // CONTROLLERRECORDABLE_H

src/libdramsys/DRAMSys/controller/ManagerIF.h

@@ -37,6 +37,9 @@
 
 #include "DRAMSys/controller/Command.h"
 
+namespace DRAMSys
+{
+
 class ManagerIF
 {
 public:
@@ -46,4 +49,6 @@ public:
     virtual ~ManagerIF() = default;
 };
 
+} // namespace DRAMSys
+
 #endif // MANAGERIF_H

src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerDDR3::CheckerDDR3(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecDDR3 *>(config.memSpec.get());
@@ -446,3 +449,5 @@ void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(sc_time_stamp());
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerDDR3 final : public CheckerIF
 {
 public:
@@ -72,4 +75,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERDDR3_H

src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerDDR4::CheckerDDR4(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecDDR4 *>(config.memSpec.get());
@@ -479,3 +482,5 @@ void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(sc_time_stamp());
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h

@@ -44,6 +44,9 @@
 #include <unordered_map>
 #include <utility>
 
+namespace DRAMSys
+{
+
 class CheckerDDR4 final : public CheckerIF
 {
 public:
@@ -78,4 +81,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERDDR4_H

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerGDDR5::CheckerGDDR5(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecGDDR5 *>(config.memSpec.get());
@@ -568,3 +571,5 @@ void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload)
     if (command == Command::REFPB)
         bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerGDDR5 final : public CheckerIF
 {
 public:
@@ -76,4 +79,6 @@ private:
     sc_core::sc_time tWRPRE;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERGDDR5_H

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerGDDR5X::CheckerGDDR5X(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecGDDR5X *>(config.memSpec.get());
@@ -572,3 +575,5 @@ void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload)
     if (command == Command::REFPB)
         bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerGDDR5X final : public CheckerIF
 {
 public:
@@ -76,4 +79,6 @@ private:
     sc_core::sc_time tWRPRE;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERGDDR5X_H

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerGDDR6::CheckerGDDR6(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecGDDR6 *>(config.memSpec.get());
@@ -585,3 +588,5 @@ void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload)
     if (command == Command::REFPB)
         bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerGDDR6 final : public CheckerIF
 {
 public:
@@ -74,4 +77,6 @@ private:
     sc_core::sc_time tWRPRE;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERGDDR6_H

src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerHBM2::CheckerHBM2(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecHBM2 *>(config.memSpec.get());
@@ -549,3 +552,5 @@ void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload)
     if (command == Command::REFPB)
         bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerHBM2 final : public CheckerIF
 {
 public:
@@ -77,4 +80,6 @@ private:
     sc_core::sc_time tWRRDR;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERHBM2_H

src/libdramsys/DRAMSys/controller/checker/CheckerIF.h

@@ -39,6 +39,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class CheckerIF
 {
 public:
@@ -48,4 +51,6 @@ public:
     virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERIF_H

src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerLPDDR4::CheckerLPDDR4(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecLPDDR4 *>(config.memSpec.get());
@@ -534,3 +537,5 @@ void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(lastCommandOnBus);
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerLPDDR4 final : public CheckerIF
 {
 public:
@@ -80,4 +83,6 @@ private:
     sc_core::sc_time tREFPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERLPDDR4_H

src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerSTTMRAM::CheckerSTTMRAM(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecSTTMRAM *>(config.memSpec.get());
@@ -402,3 +405,5 @@ void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(sc_time_stamp());
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerSTTMRAM final : public CheckerIF
 {
 public:
@@ -72,4 +75,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERSTTMRAM_H

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerWideIO::CheckerWideIO(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecWideIO *>(config.memSpec.get());
@@ -422,3 +425,5 @@ void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload)
         last2Activates[rank.ID()].push(sc_time_stamp());
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerWideIO final : public CheckerIF
 {
 public:
@@ -72,4 +75,6 @@ private:
     sc_core::sc_time tWRAPDEN;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERWIDEIO_H

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CheckerWideIO2::CheckerWideIO2(const Configuration& config)
 {
     memSpec = dynamic_cast<const MemSpecWideIO2 *>(config.memSpec.get());
@@ -500,3 +503,5 @@ void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload)
         last4Activates[rank.ID()].push(sc_time_stamp());
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h

@@ -42,6 +42,9 @@
 #include <queue>
 #include <vector>
 
+namespace DRAMSys
+{
+
 class CheckerWideIO2 final : public CheckerIF
 {
 public:
@@ -73,4 +76,6 @@ private:
     sc_core::sc_time tWRRD_R;
 };
 
+} // namespace DRAMSys
+
 #endif // CHECKERWIDEIO2_H

src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxIF.h

@@ -37,6 +37,9 @@
 
 #include "DRAMSys/controller/Command.h"
 
+namespace DRAMSys
+{
+
 class CmdMuxIF
 {
 public:
@@ -44,4 +47,6 @@ public:
     virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0;
 };
 
+} // namespace DRAMSys
+
 #endif // CMDMUXIF_H

src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.cpp

@@ -38,6 +38,9 @@
 
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 CmdMuxOldest::CmdMuxOldest(const Configuration& config) : memSpec(*config.memSpec) {}
 
 CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommands)
@@ -179,3 +182,5 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
     else
         return {Command::NOP, nullptr, scMaxTime};
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxOldest.h

@@ -38,6 +38,9 @@
 #include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
 #include "DRAMSys/configuration/Configuration.h"
 
+namespace DRAMSys
+{
+
 class CmdMuxOldest : public CmdMuxIF
 {
 public:
@@ -64,4 +67,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // CMDMUXOLDEST_H

src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.cpp

@@ -38,6 +38,9 @@
 
 using namespace sc_core;
 
+namespace DRAMSys
+{
+
 CmdMuxStrict::CmdMuxStrict(const Configuration& config) : memSpec(*config.memSpec) {}
 
 CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommands)
@@ -182,3 +185,5 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
     else
         return {Command::NOP, nullptr, scMaxTime};
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/cmdmux/CmdMuxStrict.h

@@ -38,6 +38,9 @@
 #include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
 #include "DRAMSys/configuration/Configuration.h"
 
+namespace DRAMSys
+{
+
 class CmdMuxStrict : public CmdMuxIF
 {
 public:
@@ -65,4 +68,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // CMDMUXSTRICT_H

src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.cpp

@@ -37,7 +37,12 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CommandTuple::Type PowerDownManagerDummy::getNextCommand()
 {
     return {Command::NOP, nullptr, SC_ZERO_TIME};
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerDummy.h

@@ -37,6 +37,9 @@
 
 #include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
 
+namespace DRAMSys
+{
+
 class PowerDownManagerDummy final : public PowerDownManagerIF
 {
 public:
@@ -51,4 +54,6 @@ public:
     void evaluate() override {}
 };
 
+} // namespace DRAMSys
+
 #endif // POWERDOWNMANAGERDUMMY_H

src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerIF.h

@@ -40,6 +40,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class PowerDownManagerIF : public ManagerIF
 {
 public:
@@ -48,4 +51,6 @@ public:
     virtual void triggerInterruption() = 0;
 };
 
+} // namespace DRAMSys
+
 #endif // POWERDOWNMANAGERIF_H

src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.cpp

@@ -39,6 +39,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector<BankMachine*>& bankMachinesOnRank,
         Rank rank, CheckerIF& checker)
     : bankMachinesOnRank(bankMachinesOnRank)
@@ -157,3 +160,5 @@ void PowerDownManagerStaggered::update(Command command)
             break;
     }
 }
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/powerdown/PowerDownManagerStaggered.h

@@ -41,6 +41,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class BankMachine;
 
 class PowerDownManagerStaggered final : public PowerDownManagerIF
@@ -69,4 +72,6 @@ private:
     bool enterSelfRefresh = false;
 };
 
+} // namespace DRAMSys
+
 #endif // POWERDOWNMANAGERSTAGGERED_H

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp

@@ -41,6 +41,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 RefreshManagerAllBank::RefreshManagerAllBank(const Configuration& config, std::vector<BankMachine*>& bankMachinesOnRank,
                                              PowerDownManagerIF& powerDownManager, Rank rank)
     : bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager),
@@ -223,4 +226,6 @@ void RefreshManagerAllBank::update(Command command)
 sc_time RefreshManagerAllBank::getTimeForNextTrigger()
 {
     return timeForNextTrigger;
-}
+}
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.h

@@ -44,6 +44,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class BankMachine;
 class PowerDownManagerIF;
 
@@ -78,4 +81,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // REFRESHMANAGERALLBANK_H

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.cpp

@@ -37,6 +37,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 CommandTuple::Type RefreshManagerDummy::getNextCommand()
 {
     return {Command::NOP, nullptr, SC_ZERO_TIME};
@@ -45,4 +48,6 @@ CommandTuple::Type RefreshManagerDummy::getNextCommand()
 sc_time RefreshManagerDummy::getTimeForNextTrigger()
 {
     return scMaxTime;
-}
+}
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerDummy.h

@@ -39,6 +39,9 @@
 
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class RefreshManagerDummy final : public RefreshManagerIF
 {
 public:
@@ -50,4 +53,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // REFRESHMANAGERDUMMY_H

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerIF.h

@@ -42,6 +42,9 @@
 #include <cmath>
 #include <systemc>
 
+namespace DRAMSys
+{
+
 class RefreshManagerIF : public ManagerIF
 {
 public:
@@ -77,4 +80,6 @@ protected:
     }
 };
 
+} // namespace DRAMSys
+
 #endif // REFRESHMANAGERIF_H

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.cpp

@@ -40,6 +40,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 RefreshManagerPer2Bank::RefreshManagerPer2Bank(const Configuration& config,
                                                std::vector<BankMachine*>& bankMachinesOnRank,
                                                PowerDownManagerIF& powerDownManager, Rank rank)
@@ -246,4 +249,6 @@ void RefreshManagerPer2Bank::update(Command command)
 sc_time RefreshManagerPer2Bank::getTimeForNextTrigger()
 {
     return timeForNextTrigger;
-}
+}
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPer2Bank.h

@@ -46,6 +46,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class BankMachine;
 class PowerDownManagerIF;
 
@@ -83,4 +86,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // REFRESHMANAGERPER2BANK_H

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.cpp

@@ -40,6 +40,9 @@
 using namespace sc_core;
 using namespace tlm;
 
+namespace DRAMSys
+{
+
 RefreshManagerPerBank::RefreshManagerPerBank(const Configuration& config, std::vector<BankMachine*>& bankMachinesOnRank,
                                              PowerDownManagerIF& powerDownManager, Rank rank)
     : powerDownManager(powerDownManager), memSpec(*config.memSpec),
@@ -205,4 +208,6 @@ void RefreshManagerPerBank::update(Command command)
 sc_time RefreshManagerPerBank::getTimeForNextTrigger()
 {
     return timeForNextTrigger;
-}
+}
+
+} // namespace DRAMSys

src/libdramsys/DRAMSys/controller/refresh/RefreshManagerPerBank.h

@@ -46,6 +46,9 @@
 #include <systemc>
 #include <tlm>
 
+namespace DRAMSys
+{
+
 class BankMachine;
 class PowerDownManagerIF;
 
@@ -82,4 +85,6 @@ private:
     const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
 };
 
+} // namespace DRAMSys
+
 #endif // REFRESHMANAGERPERBANK_H