253 lines
8.6 KiB
C++
253 lines
8.6 KiB
C++
/*
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* Copyright (c) 2015, Technische Universität Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Janik Schlemminger
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* Robert Gernhardt
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* Matthias Jung
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* Lukas Steiner
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*/
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#include "Command.h"
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#include <array>
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using namespace tlm;
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#ifdef DRAMPOWER
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using namespace DRAMPower;
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#endif
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namespace DRAMSys
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{
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bool phaseHasDataStrobe(tlm::tlm_phase phase)
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{
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return (phase >= BEGIN_RD && phase <= BEGIN_WRA);
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}
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bool isPowerDownEntryPhase(tlm::tlm_phase phase)
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{
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return (phase >= BEGIN_PDNA && phase <= BEGIN_SREF);
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}
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bool isPowerDownExitPhase(tlm::tlm_phase phase)
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{
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return (phase >= END_PDNA && phase <= END_SREF);
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}
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bool isFixedCommandPhase(tlm::tlm_phase phase)
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{
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return (phase >= BEGIN_NOP && phase <= BEGIN_RFMAB);
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}
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bool isRefreshCommandPhase(tlm::tlm_phase phase)
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{
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return (phase == BEGIN_REFPB || phase == BEGIN_REFP2B || phase == BEGIN_REFSB || phase == BEGIN_REFAB
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|| phase == BEGIN_RFMPB || phase == BEGIN_RFMP2B || phase == BEGIN_RFMSB || phase == BEGIN_RFMAB);
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}
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Command::Command(Command::Type type) : type(type) {}
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Command::Command(tlm_phase phase)
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{
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assert(phase >= BEGIN_NOP && phase <= END_SREF);
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static constexpr std::array<Command::Type, Command::Type::END_ENUM> commandOfPhase =
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{
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Command::NOP, // 0
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Command::RD, // 1
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Command::WR, // 2
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Command::RDA, // 3
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Command::WRA, // 4
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Command::ACT, // 5
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Command::PREPB, // 6
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Command::REFPB, // 7
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Command::RFMPB, // 8
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Command::REFP2B, // 9
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Command::RFMP2B, // 10
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Command::PRESB, // 11
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Command::REFSB, // 12
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Command::RFMSB, // 13
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Command::PREAB, // 14
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Command::REFAB, // 15
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Command::RFMAB, // 16
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Command::PDEA, // 17
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Command::PDEP, // 18
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Command::SREFEN, // 19
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Command::PDXA, // 20
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Command::PDXP, // 21
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Command::SREFEX // 22
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};
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type = commandOfPhase[phase - BEGIN_NOP];
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}
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std::string Command::toString() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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static std::array<std::string, Command::Type::END_ENUM> stringOfCommand =
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{
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"NOP", // 0
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"RD", // 1
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"WR", // 2
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"RDA", // 3
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"WRA", // 4
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"ACT", // 5
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"PREPB", // 6
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"REFPB", // 7
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"RFMPB", // 8
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"REFP2B", // 9
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"RFMP2B", // 10
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"PRESB", // 11
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"REFSB", // 12
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"RFMSB", // 13
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"PREAB", // 14
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"REFAB", // 15
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"RFMAB", // 16
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"PDEA", // 17
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"PDEP", // 18
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"SREFEN", // 19
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"PDXA", // 20
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"PDXP", // 21
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"SREFEX" // 22
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};
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return stringOfCommand[type];
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}
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unsigned Command::numberOfCommands()
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{
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return Type::END_ENUM;
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}
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tlm_phase Command::toPhase() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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static std::array<tlm_phase, Command::Type::END_ENUM> phaseOfCommand =
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{
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BEGIN_NOP, // 0
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BEGIN_RD, // 1
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BEGIN_WR, // 2
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BEGIN_RDA, // 3
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BEGIN_WRA, // 4
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BEGIN_ACT, // 5
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BEGIN_PREPB, // 6
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BEGIN_REFPB, // 7
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BEGIN_RFMPB, // 8
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BEGIN_REFP2B, // 9
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BEGIN_RFMP2B, // 10
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BEGIN_PRESB, // 11
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BEGIN_REFSB, // 12
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BEGIN_RFMSB, // 13
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BEGIN_PREAB, // 14
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BEGIN_REFAB, // 15
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BEGIN_RFMAB, // 16
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BEGIN_PDNA, // 17
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BEGIN_PDNP, // 18
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BEGIN_SREF, // 19
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END_PDNA, // 20
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END_PDNP, // 21
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END_SREF // 22
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};
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return phaseOfCommand[type];
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}
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#ifdef DRAMPOWER
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MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
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{
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// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
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assert(phase >= BEGIN_NOP && phase <= END_SREF);
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static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand =
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{
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MemCommand::NOP, // 0
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MemCommand::RD, // 1
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MemCommand::WR, // 2
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MemCommand::RDA, // 3
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MemCommand::WRA, // 4
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MemCommand::ACT, // 5
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MemCommand::PRE, // 6, PREPB
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MemCommand::REFB, // 7, REFPB
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MemCommand::NOP, // 8, RFMPB
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MemCommand::NOP, // 9, REFP2B
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MemCommand::NOP, // 10, RFMP2B
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MemCommand::NOP, // 11, PRESB
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MemCommand::NOP, // 12, REFSB
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MemCommand::NOP, // 13, RFMSB
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MemCommand::PREA, // 14, PREAB
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MemCommand::REF, // 15, REFAB
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MemCommand::NOP, // 16, RFMAB
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MemCommand::PDN_S_ACT, // 17
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MemCommand::PDN_S_PRE, // 18
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MemCommand::SREN, // 19
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MemCommand::PUP_ACT, // 20
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MemCommand::PUP_PRE, // 21
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MemCommand::SREX // 22
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};
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return phaseOfCommand[phase - BEGIN_NOP];
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}
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#endif
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bool Command::isBankCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type <= Command::RFMPB);
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}
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bool Command::is2BankCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type >= Command::REFP2B && type <= Command::RFMP2B);
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}
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bool Command::isGroupCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type >= Command::PRESB && type <= Command::RFMSB);
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}
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bool Command::isRankCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type >= Command::PREAB);
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}
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bool Command::isCasCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type <= Command::WRA);
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}
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bool Command::isRasCommand() const
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{
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assert(type >= Command::NOP && type <= Command::SREFEX);
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return (type >= Command::ACT);
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}
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} // namespace DRAMSys
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