175 lines
7.4 KiB
C++
175 lines
7.4 KiB
C++
/*
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* Copyright (c) 2019, Technische Universität Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Lukas Steiner
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* Derek Christ
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*/
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#include "MemSpecHBM2.h"
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#include "DRAMSys/common/utils.h"
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#include <iostream>
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using namespace sc_core;
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using namespace tlm;
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namespace DRAMSys
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{
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MemSpecHBM2::MemSpecHBM2(const DRAMSys::Config::MemSpec &memSpec)
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: MemSpec(memSpec, MemoryType::HBM2,
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memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
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memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
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memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
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memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
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memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
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memSpec.memarchitecturespec.entries.at("nbrOfBanks")
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/ memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
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memSpec.memarchitecturespec.entries.at("nbrOfBanks")
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* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
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memSpec.memarchitecturespec.entries.at("nbrOfBankGroups")
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* memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
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memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
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tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
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tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
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tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
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tRCDRD (tCK * memSpec.memtimingspec.entries.at("RCDRD")),
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tRCDWR (tCK * memSpec.memtimingspec.entries.at("RCDWR")),
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tRRDL (tCK * memSpec.memtimingspec.entries.at("RRDL")),
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tRRDS (tCK * memSpec.memtimingspec.entries.at("RRDS")),
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tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
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tRTP (tCK * memSpec.memtimingspec.entries.at("RTP")),
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tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
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tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
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tWL (tCK * memSpec.memtimingspec.entries.at("WL")),
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tPL (tCK * memSpec.memtimingspec.entries.at("PL")),
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tWR (tCK * memSpec.memtimingspec.entries.at("WR")),
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tCCDL (tCK * memSpec.memtimingspec.entries.at("CCDL")),
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tCCDS (tCK * memSpec.memtimingspec.entries.at("CCDS")),
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tWTRL (tCK * memSpec.memtimingspec.entries.at("WTRL")),
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tWTRS (tCK * memSpec.memtimingspec.entries.at("WTRS")),
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tRTW (tCK * memSpec.memtimingspec.entries.at("RTW")),
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tXP (tCK * memSpec.memtimingspec.entries.at("XP")),
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tCKE (tCK * memSpec.memtimingspec.entries.at("CKE")),
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tPD (tCKE),
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tCKESR (tCKE + tCK),
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tXS (tCK * memSpec.memtimingspec.entries.at("XS")),
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tRFC (tCK * memSpec.memtimingspec.entries.at("RFC")),
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tRFCSB (tCK * memSpec.memtimingspec.entries.at("RFCSB")),
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tRREFD (tCK * memSpec.memtimingspec.entries.at("RREFD")),
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tREFI (tCK * memSpec.memtimingspec.entries.at("REFI")),
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tREFISB (tCK * memSpec.memtimingspec.entries.at("REFISB"))
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{
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commandLengthInCycles[Command::ACT] = 2;
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uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
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uint64_t deviceSizeBytes = deviceSizeBits / 8;
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memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
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std::cout << headline << std::endl;
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std::cout << "Memory Configuration:" << std::endl << std::endl;
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std::cout << " Memory type: " << "HBM2" << std::endl;
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std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
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std::cout << " Channels: " << numberOfChannels << std::endl;
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std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl;
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std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl;
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std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl;
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std::cout << " Rows per bank: " << rowsPerBank << std::endl;
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std::cout << " Columns per row: " << columnsPerRow << std::endl;
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std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl;
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std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl;
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std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl;
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std::cout << std::endl;
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}
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sc_time MemSpecHBM2::getRefreshIntervalAB() const
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{
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return tREFI;
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}
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sc_time MemSpecHBM2::getRefreshIntervalPB() const
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{
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return tREFISB;
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}
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bool MemSpecHBM2::hasRasAndCasBus() const
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{
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return true;
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}
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sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload &payload) const
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{
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if (command == Command::PREPB || command == Command::PREAB)
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return tRP;
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else if (command == Command::ACT)
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{
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if (payload.get_command() == TLM_READ_COMMAND)
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return tRCDRD + tCK;
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else
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return tRCDWR + tCK;
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}
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else if (command == Command::RD)
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return tRL + tDQSCK + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFAB)
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return tRFC;
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else if (command == Command::REFPB)
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return tRFCSB;
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else
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{
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SC_REPORT_FATAL("getExecutionTime",
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"command not known or command doesn't have a fixed execution time");
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return SC_ZERO_TIME;
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}
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}
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TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
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{
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if (command == Command::RD || command == Command::RDA)
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return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
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else if (command == Command::WR || command == Command::WRA)
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return {tWL, tWL + burstDuration};
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else
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{
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SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
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return {};
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}
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}
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} // namespace DRAMSys
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